Richard Henderson e7207a9971 * target/i386: SEV: fix incorrect property name ... * target/i386: tcg: fix VSIB decode with XMM/YMM{4,12} -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmawwjoUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroO+kgf/SIOaF14Ozw6w33zddDiuK969ouNR 00hC17p0acVl3KwmbXBJp2CXtc4TcZwLEg6y2KrActEVg2CaFFjGx9wJUnTGOL/D 3Nhp3ipsExv+rFQuQvV9k/BeAVG0G9YoTZtQJVQvLPL/LYJ76h2JlVamjr9rsuKy hsVeHX6Xl6ad6mtM1hSFBonJzfGK08rKQPTnALfB0raFLmSHWleg9Xzs0r1YiuO2 SsGVr0NF369pZA2U0Y/tcw0RIRIikXfVYTX5+o9H6RzEqbqaOh3j9upLYSWym6LN cedTxjNFJdxZReR/VE1kAys3s2pE8k+yiQIBGzfwo4fN6hukJZGCtwrVmw== =2tkB -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * target/i386: SEV: fix incorrect property name * target/i386: tcg: fix VSIB decode with XMM/YMM{4,12} # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmawwjoUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroO+kgf/SIOaF14Ozw6w33zddDiuK969ouNR # 00hC17p0acVl3KwmbXBJp2CXtc4TcZwLEg6y2KrActEVg2CaFFjGx9wJUnTGOL/D # 3Nhp3ipsExv+rFQuQvV9k/BeAVG0G9YoTZtQJVQvLPL/LYJ76h2JlVamjr9rsuKy # hsVeHX6Xl6ad6mtM1hSFBonJzfGK08rKQPTnALfB0raFLmSHWleg9Xzs0r1YiuO2 # SsGVr0NF369pZA2U0Y/tcw0RIRIikXfVYTX5+o9H6RzEqbqaOh3j9upLYSWym6LN # cedTxjNFJdxZReR/VE1kAys3s2pE8k+yiQIBGzfwo4fN6hukJZGCtwrVmw== # =2tkB # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Aug 2024 10:14:50 PM AEST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386: Fix VSIB decode target/i386: SEV: fix mismatch in vcek-disabled property name Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-08-06 08:02:34 +10:00
..
alpha	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
arm	hvf: arm: Fix hvf_sysreg_read_cp() call	2024-08-03 07:24:12 +10:00
avr	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
cris	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
hexagon	target/hexagon/imported/mmvec: Fix superfluous trailing semicolon	2024-07-17 14:04:15 +03:00
hppa	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
i386	target/i386: Fix VSIB decode	2024-08-05 14:14:47 +02:00
loongarch	target/loongarch: Fix helper_lddir() a CID INTEGER_OVERFLOW issue	2024-07-24 16:52:18 +08:00
m68k	target/m68k: avoid shift into sign bit in dump_address_map()	2024-07-29 16:58:58 +01:00
microblaze	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
mips	target/mips: Restrict semihosting to TCG	2024-07-22 09:38:10 +01:00
openrisc	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
ppc	target/ppc: Remove includes from mmu-book3s-v3.h	2024-07-26 09:51:34 +10:00
riscv	accel/tcg: Export set/clear_helper_retaddr	2024-07-23 15:19:39 +10:00
rx	target/rx: Use target_ulong for address in LI	2024-07-28 14:13:05 +10:00
s390x	target/s390x: move @deprecated-props to CpuModelExpansion Info	2024-07-29 21:47:16 +02:00
sh4	target/sh4: Avoid shift into sign bit in update_itlb_use()	2024-07-29 17:00:20 +01:00
sparc	sparc/ldst_helper: make range overlap check more readable	2024-07-23 20:30:36 +02:00
tricore	target/tricore: Use unsigned types for bitops in helper_eq_b()	2024-07-29 16:57:27 +01:00
xtensa	target/xtensa: Correct assert condition in handle_interrupt()	2024-08-01 10:59:01 +01:00
Kconfig	meson: make target endianneess available to Kconfig	2024-05-03 15:47:47 +02:00
meson.build	exec: Expose 'target_page.h' API to user emulation	2024-04-26 15:28:11 +02:00