LIU Zhiwei eee2d61e20 target/riscv: Pass the same value to oprsz and maxsz. ... Since commit e2e7168a21, if oprsz is still zero(as we don't use this field), simd_desc will trigger an assert. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation. Here we pass the value to maxsz and oprsz to bypass the assert. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-06-08 09:59:43 +10:00
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trans_privileged.c.inc	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
trans_rva.c.inc	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvd.c.inc	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvf.c.inc	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvh.c.inc	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvi.c.inc	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvm.c.inc	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
trans_rvv.c.inc	target/riscv: Pass the same value to oprsz and maxsz.	2021-06-08 09:59:43 +10:00