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ee48fef06c
The Aspeed SMC device model use to have a 'sdram_base' property. It
was removed by commit d177892d4a ("aspeed/smc: Remove unused
"sdram-base" property") because previous changes simplified the DMA
transaction model to use an offset in RAM and not the physical
address.
The AST2700 SoC has larger address space (64-bit) and a new register
DMA DRAM Side Address High Part (0x7C) is introduced to deal with the
high bits of the DMA address. To be able to compute the offset of the
DMA transaction, as done on the other SoCs, we will need to know where
the DRAM is mapped in the address space. Re-introduce a "dram-base"
property to hold this value.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*
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* ASPEED AST2400 SMC Controller (SPI Flash Only)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef ASPEED_SMC_H
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#define ASPEED_SMC_H
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#include "hw/ssi/ssi.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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struct AspeedSMCState;
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struct AspeedSMCClass;
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#define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
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struct AspeedSMCFlash {
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SysBusDevice parent_obj;
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struct AspeedSMCState *controller;
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struct AspeedSMCClass *asc;
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uint8_t cs;
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MemoryRegion mmio;
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};
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#define TYPE_ASPEED_SMC "aspeed.smc"
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OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)
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#define ASPEED_SMC_R_MAX (0x100 / 4)
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#define ASPEED_SMC_CS_MAX 5
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struct AspeedSMCState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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MemoryRegion mmio_flash_container;
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MemoryRegion mmio_flash;
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qemu_irq irq;
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qemu_irq *cs_lines;
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bool inject_failure;
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SSIBus *spi;
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uint32_t regs[ASPEED_SMC_R_MAX];
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/* depends on the controller type */
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uint8_t r_conf;
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uint8_t r_ce_ctrl;
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uint8_t r_ctrl0;
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uint8_t r_timings;
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uint8_t conf_enable_w0;
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AddressSpace flash_as;
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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uint64_t dram_base;
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AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX];
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uint8_t snoop_index;
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uint8_t snoop_dummies;
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};
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typedef struct AspeedSegments {
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hwaddr addr;
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uint32_t size;
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} AspeedSegments;
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struct AspeedSMCClass {
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SysBusDeviceClass parent_obj;
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uint8_t r_conf;
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uint8_t r_ce_ctrl;
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uint8_t r_ctrl0;
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uint8_t r_timings;
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uint8_t nregs_timings;
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uint8_t conf_enable_w0;
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uint8_t cs_num_max;
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const uint32_t *resets;
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const AspeedSegments *segments;
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uint32_t segment_addr_mask;
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hwaddr flash_window_base;
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uint32_t flash_window_size;
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uint32_t features;
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hwaddr dma_flash_mask;
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hwaddr dma_dram_mask;
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uint32_t nregs;
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uint32_t (*segment_to_reg)(const AspeedSMCState *s,
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const AspeedSegments *seg);
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void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg,
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AspeedSegments *seg);
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void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
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int (*addr_width)(const AspeedSMCState *s);
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};
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#endif /* ASPEED_SMC_H */
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