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ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
42 lines
1 KiB
C
42 lines
1 KiB
C
#ifndef HW_ARM_ALLWINNER_A10_H
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#define HW_ARM_ALLWINNER_A10_H
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#include "qemu/error-report.h"
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#include "hw/char/serial.h"
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#include "hw/arm/boot.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/intc/allwinner-a10-pic.h"
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#include "hw/net/allwinner_emac.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "sysemu/sysemu.h"
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#include "target/arm/cpu.h"
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#define AW_A10_PIC_REG_BASE 0x01c20400
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#define AW_A10_PIT_REG_BASE 0x01c20c00
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#define AW_A10_UART0_REG_BASE 0x01c28000
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#define AW_A10_EMAC_BASE 0x01c0b000
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#define AW_A10_SATA_BASE 0x01c18000
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#define AW_A10_SDRAM_BASE 0x40000000
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#define TYPE_AW_A10 "allwinner-a10"
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#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
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typedef struct AwA10State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU cpu;
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qemu_irq irq[AW_A10_PIC_INT_NR];
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AwA10PITState timer;
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AwA10PICState intc;
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AwEmacState emac;
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AllwinnerAHCIState sata;
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MemoryRegion sram_a;
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} AwA10State;
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#endif
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