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The GGC register at 0x50 of pci config space is a mirror of the same
register at 0x108040 of mmio bar0 [1]. i915 driver also reads that
register from mmio bar0 instead of config space. As GGC is programmed
and emulated by qemu, the mmio address should also be emulated, in the
same way of BDSM register.
[1] 4.1.28, 12th Generation Intel Core Processors Datasheet Volume 2
https://www.intel.com/content/www/us/en/content-details/655259
Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Link: https://lore.kernel.org/r/20241206122749.9893-9-tomitamoeko@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
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| .. | ||
| amd-xgbe.c | ||
| ap.c | ||
| calxeda-xgmac.c | ||
| ccw.c | ||
| common.c | ||
| container-base.c | ||
| container.c | ||
| cpr.c | ||
| display.c | ||
| helpers.c | ||
| igd.c | ||
| iommufd.c | ||
| Kconfig | ||
| meson.build | ||
| migration.c | ||
| pci-quirks.c | ||
| pci.c | ||
| pci.h | ||
| platform.c | ||
| spapr.c | ||
| trace-events | ||
| trace.h | ||