mirror of
https://github.com/Motorhead1991/qemu.git
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e972bf22f6
This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
399 lines
16 KiB
C
399 lines
16 KiB
C
/*
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* RISC-V Vector Crypto Extension Helpers for QEMU.
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*
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* Copyright (C) 2023 SiFive, Inc.
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* Written by Codethink Ltd and SiFive.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "qemu/bitops.h"
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#include "qemu/bswap.h"
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#include "cpu.h"
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#include "crypto/aes.h"
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#include "crypto/aes-round.h"
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#include "exec/memop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "internals.h"
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#include "vector_internals.h"
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static uint64_t clmul64(uint64_t y, uint64_t x)
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{
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uint64_t result = 0;
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for (int j = 63; j >= 0; j--) {
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if ((y >> j) & 1) {
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result ^= (x << j);
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}
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}
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return result;
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}
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static uint64_t clmulh64(uint64_t y, uint64_t x)
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{
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uint64_t result = 0;
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for (int j = 63; j >= 1; j--) {
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if ((y >> j) & 1) {
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result ^= (x >> (64 - j));
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}
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}
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return result;
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}
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RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64)
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GEN_VEXT_VV(vclmul_vv, 8)
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RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64)
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GEN_VEXT_VX(vclmul_vx, 8)
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RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
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GEN_VEXT_VV(vclmulh_vv, 8)
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RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
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GEN_VEXT_VX(vclmulh_vx, 8)
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RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8)
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RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16)
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RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32)
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RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64)
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GEN_VEXT_VV(vror_vv_b, 1)
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GEN_VEXT_VV(vror_vv_h, 2)
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GEN_VEXT_VV(vror_vv_w, 4)
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GEN_VEXT_VV(vror_vv_d, 8)
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RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8)
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RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16)
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RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32)
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RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64)
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GEN_VEXT_VX(vror_vx_b, 1)
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GEN_VEXT_VX(vror_vx_h, 2)
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GEN_VEXT_VX(vror_vx_w, 4)
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GEN_VEXT_VX(vror_vx_d, 8)
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RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8)
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RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16)
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RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32)
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RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64)
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GEN_VEXT_VV(vrol_vv_b, 1)
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GEN_VEXT_VV(vrol_vv_h, 2)
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GEN_VEXT_VV(vrol_vv_w, 4)
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GEN_VEXT_VV(vrol_vv_d, 8)
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RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8)
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RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16)
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RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32)
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RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64)
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GEN_VEXT_VX(vrol_vx_b, 1)
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GEN_VEXT_VX(vrol_vx_h, 2)
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GEN_VEXT_VX(vrol_vx_w, 4)
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GEN_VEXT_VX(vrol_vx_d, 8)
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static uint64_t brev8(uint64_t val)
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{
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val = ((val & 0x5555555555555555ull) << 1) |
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((val & 0xAAAAAAAAAAAAAAAAull) >> 1);
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val = ((val & 0x3333333333333333ull) << 2) |
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((val & 0xCCCCCCCCCCCCCCCCull) >> 2);
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val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4) |
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((val & 0xF0F0F0F0F0F0F0F0ull) >> 4);
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return val;
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}
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RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8)
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RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8)
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RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8)
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RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8)
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GEN_VEXT_V(vbrev8_v_b, 1)
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GEN_VEXT_V(vbrev8_v_h, 2)
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GEN_VEXT_V(vbrev8_v_w, 4)
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GEN_VEXT_V(vbrev8_v_d, 8)
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#define DO_IDENTITY(a) (a)
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RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY)
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RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16)
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RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32)
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RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64)
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GEN_VEXT_V(vrev8_v_b, 1)
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GEN_VEXT_V(vrev8_v_h, 2)
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GEN_VEXT_V(vrev8_v_w, 4)
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GEN_VEXT_V(vrev8_v_d, 8)
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#define DO_ANDN(a, b) ((a) & ~(b))
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RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN)
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RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN)
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RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN)
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RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN)
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GEN_VEXT_VV(vandn_vv_b, 1)
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GEN_VEXT_VV(vandn_vv_h, 2)
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GEN_VEXT_VV(vandn_vv_w, 4)
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GEN_VEXT_VV(vandn_vv_d, 8)
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RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN)
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RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN)
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RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN)
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RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN)
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GEN_VEXT_VX(vandn_vx_b, 1)
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GEN_VEXT_VX(vandn_vx_h, 2)
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GEN_VEXT_VX(vandn_vx_w, 4)
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GEN_VEXT_VX(vandn_vx_d, 8)
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RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8)
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RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16)
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RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32)
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RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64)
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GEN_VEXT_V(vbrev_v_b, 1)
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GEN_VEXT_V(vbrev_v_h, 2)
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GEN_VEXT_V(vbrev_v_w, 4)
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GEN_VEXT_V(vbrev_v_d, 8)
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RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8)
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RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16)
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RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32)
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RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64)
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GEN_VEXT_V(vclz_v_b, 1)
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GEN_VEXT_V(vclz_v_h, 2)
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GEN_VEXT_V(vclz_v_w, 4)
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GEN_VEXT_V(vclz_v_d, 8)
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RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8)
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RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16)
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RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32)
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RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64)
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GEN_VEXT_V(vctz_v_b, 1)
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GEN_VEXT_V(vctz_v_h, 2)
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GEN_VEXT_V(vctz_v_w, 4)
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GEN_VEXT_V(vctz_v_d, 8)
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RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8)
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RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16)
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RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32)
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RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64)
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GEN_VEXT_V(vcpop_v_b, 1)
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GEN_VEXT_V(vcpop_v_h, 2)
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GEN_VEXT_V(vcpop_v_w, 4)
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GEN_VEXT_V(vcpop_v_d, 8)
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#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1)))
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RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL)
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RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL)
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RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL)
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GEN_VEXT_VV(vwsll_vv_b, 2)
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GEN_VEXT_VV(vwsll_vv_h, 4)
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GEN_VEXT_VV(vwsll_vv_w, 8)
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RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL)
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RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL)
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RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
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GEN_VEXT_VX(vwsll_vx_b, 2)
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GEN_VEXT_VX(vwsll_vx_h, 4)
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GEN_VEXT_VX(vwsll_vx_w, 8)
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void HELPER(egs_check)(uint32_t egs, CPURISCVState *env)
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{
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uint32_t vl = env->vl;
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uint32_t vstart = env->vstart;
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if (vl % egs != 0 || vstart % egs != 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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}
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static inline void xor_round_key(AESState *round_state, AESState *round_key)
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{
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round_state->v = round_state->v ^ round_key->v;
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}
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#define GEN_ZVKNED_HELPER_VV(NAME, ...) \
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void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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uint32_t vl = env->vl; \
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uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
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uint32_t vta = vext_vta(desc); \
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\
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
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AESState round_key; \
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round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
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round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
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AESState round_state; \
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round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
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round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
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__VA_ARGS__; \
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*((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
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*((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
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} \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
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}
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#define GEN_ZVKNED_HELPER_VS(NAME, ...) \
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void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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uint32_t vl = env->vl; \
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uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
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uint32_t vta = vext_vta(desc); \
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\
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
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AESState round_key; \
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round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
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round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
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AESState round_state; \
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round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
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round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
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__VA_ARGS__; \
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*((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
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*((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
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} \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
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}
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GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state,
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&round_state,
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&round_key,
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false);)
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GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);)
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void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
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CPURISCVState *env, uint32_t desc)
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{
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uint32_t *vd = vd_vptr;
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uint32_t *vs2 = vs2_vptr;
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uint32_t vl = env->vl;
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uint32_t total_elems = vext_get_total_elems(env, desc, 4);
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uint32_t vta = vext_vta(desc);
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uimm &= 0b1111;
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if (uimm > 10 || uimm == 0) {
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uimm ^= 0b1000;
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}
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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uint32_t rk[8], tmp;
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static const uint32_t rcon[] = {
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0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
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0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
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};
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rk[0] = vs2[i * 4 + H4(0)];
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rk[1] = vs2[i * 4 + H4(1)];
|
|
rk[2] = vs2[i * 4 + H4(2)];
|
|
rk[3] = vs2[i * 4 + H4(3)];
|
|
tmp = ror32(rk[3], 8);
|
|
|
|
rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
|
|
((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
|
|
((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
|
|
((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
|
|
^ rcon[uimm - 1];
|
|
rk[5] = rk[1] ^ rk[4];
|
|
rk[6] = rk[2] ^ rk[5];
|
|
rk[7] = rk[3] ^ rk[6];
|
|
|
|
vd[i * 4 + H4(0)] = rk[4];
|
|
vd[i * 4 + H4(1)] = rk[5];
|
|
vd[i * 4 + H4(2)] = rk[6];
|
|
vd[i * 4 + H4(3)] = rk[7];
|
|
}
|
|
env->vstart = 0;
|
|
/* set tail elements to 1s */
|
|
vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
|
|
}
|
|
|
|
void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
|
|
CPURISCVState *env, uint32_t desc)
|
|
{
|
|
uint32_t *vd = vd_vptr;
|
|
uint32_t *vs2 = vs2_vptr;
|
|
uint32_t vl = env->vl;
|
|
uint32_t total_elems = vext_get_total_elems(env, desc, 4);
|
|
uint32_t vta = vext_vta(desc);
|
|
|
|
uimm &= 0b1111;
|
|
if (uimm > 14 || uimm < 2) {
|
|
uimm ^= 0b1000;
|
|
}
|
|
|
|
for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
|
|
uint32_t rk[12], tmp;
|
|
static const uint32_t rcon[] = {
|
|
0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
|
|
0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
|
|
};
|
|
|
|
rk[0] = vd[i * 4 + H4(0)];
|
|
rk[1] = vd[i * 4 + H4(1)];
|
|
rk[2] = vd[i * 4 + H4(2)];
|
|
rk[3] = vd[i * 4 + H4(3)];
|
|
rk[4] = vs2[i * 4 + H4(0)];
|
|
rk[5] = vs2[i * 4 + H4(1)];
|
|
rk[6] = vs2[i * 4 + H4(2)];
|
|
rk[7] = vs2[i * 4 + H4(3)];
|
|
|
|
if (uimm % 2 == 0) {
|
|
tmp = ror32(rk[7], 8);
|
|
rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
|
|
((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
|
|
((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
|
|
((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
|
|
^ rcon[(uimm - 1) / 2];
|
|
} else {
|
|
rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) |
|
|
((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) |
|
|
((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) |
|
|
((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0));
|
|
}
|
|
rk[9] = rk[1] ^ rk[8];
|
|
rk[10] = rk[2] ^ rk[9];
|
|
rk[11] = rk[3] ^ rk[10];
|
|
|
|
vd[i * 4 + H4(0)] = rk[8];
|
|
vd[i * 4 + H4(1)] = rk[9];
|
|
vd[i * 4 + H4(2)] = rk[10];
|
|
vd[i * 4 + H4(3)] = rk[11];
|
|
}
|
|
env->vstart = 0;
|
|
/* set tail elements to 1s */
|
|
vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
|
|
}
|