Peter Maydell e3955ae93f Third RISC-V PR for 6.1 release ... - Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmDUc9oACgkQIeENKd+X cFQnJQf/YJ1DcCc5HKnJD7dKOO7auWGrjcBydVLZpCKT/sBYO2m4+LcUoCkndJst z2awR2sL6zgTqkpKTFJzENBKcXf0NOAvGvuvAznPQosvW26NhY20EsWHgRxn79DF 2CvFChD4J/aBZa/JwP7232CebsD2IqKn89gP5u6ldFNH36EGpzBRjFOroXLu98x3 arhr7AoyhTTpxcWkWuLW9YVwqZQ8xKKCVTMuqMC8SRI48FUB5+ndy3pTQqIjdoCg U0wfJIrmPBakw3ik0nbNd47Lu/yxCQMU/O4M/flSbbC1GpomiUotlap9O3LlvNYo 7VeF8eS3/7Okn2/5jEwuFES+MmtUSQ== =zVjG -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging Third RISC-V PR for 6.1 release - Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer # gpg: Signature made Thu 24 Jun 2021 13:00:26 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210624-2: hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/timer: Initial commit of Ibex Timer hw/char/ibex_uart: Make the register layout private hw/char: QOMify sifive_uart hw/char: Consistent function names for sifive_uart target/riscv: gdbstub: Fix dynamic CSR XML generation target/riscv: Use target_ulong for the DisasContext misa Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-06-25 17:05:22 +01:00
..
authz	Prefer 'on' | 'off' over 'yes' | 'no' for bool options	2021-01-29 17:07:53 +00:00
block	nbd/client-connection: add option for non-blocking connection attempt	2021-06-18 12:21:22 -05:00
chardev	chardev: Fix yank with the chardev-change case	2021-04-01 15:27:44 +04:00
crypto	crypto: add reload for QCryptoTLSCredsClass	2021-03-23 08:48:21 +01:00
disas	Drop the deprecated lm32 target	2021-05-12 18:20:25 +02:00
exec	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
fpu	Remove leading underscores from QEMU defines	2021-06-21 05:49:01 +02:00
hw	Third RISC-V PR for 6.1 release	2021-06-25 17:05:22 +01:00
io	io: add qio_channel_readv_full_all_eof & qio_channel_readv_full_all helpers	2021-02-10 09:23:28 +00:00
libdecnumber	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
migration	cpu: Move CPUClass::vmsd to SysemuCPUOps	2021-05-26 15:33:59 -07:00
monitor	hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds	2021-06-08 20:18:26 +01:00
net	vhost-vdpa: remove the unused vhost_vdpa_get_acked_features()	2021-06-11 10:30:13 +08:00
qapi	vl: plumb keyval-based options into -readconfig	2021-06-04 13:50:04 +02:00
qemu	plugins/api: expose symbol lookup to plugins	2021-06-25 10:08:37 +01:00
qom	qom: move user_creatable_add_opts logic to vl.c and QAPIfy it	2021-03-19 10:18:17 +01:00
scsi	scsi: inline sg_io_sense_from_errno() into the callers.	2021-03-06 11:42:56 +01:00
semihosting	semihosting: Move include/hw/semihosting/ -> include/semihosting/	2021-03-10 15:34:12 +00:00
standard-headers	Update Linux headers to 5.13-rc4	2021-06-17 14:11:06 -04:00
sysemu	* avoid deprecation warnings for SASL on macOS 10.11 or newer	2021-06-17 15:43:26 +01:00
tcg	target-arm queue:	2021-06-24 15:00:34 +01:00
ui	ui/cocoa: Add clipboard support	2021-06-23 14:26:04 +02:00
user	Remove leading underscores from QEMU defines	2021-06-21 05:49:01 +02:00
elf.h	linux-user: elf: s390x: Prepare for Vector enhancements facility	2021-06-21 08:48:21 +02:00
glib-compat.h	configure: bump min required glib version to 2.56	2021-06-02 09:11:32 +02:00
qemu-common.h	qemu-common.h: Update copyright string to 2021	2021-03-09 22:19:24 +01:00
qemu-io.h	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
trace-tcg.h	trace: get rid of generated-events.h/generated-events.c	2016-10-12 09:54:52 +02:00