Paolo Bonzini e2e0828e0f rust: pl011: extend registers to 32 bits ... The PL011 Technical Reference Manual lists the "real" size of the registers in table 3-1, and only rounds up to the next byte when describing the registers; for example, UARTDR is listed as having width 12/8 (12 bits read, 8 written) and only bits 15:0 are listed in "Table 3-2 UARTDR Register". However, in practice these are 32-bit registers, accessible only through 32-bit MMIO accesses; preserving the fiction that they're smaller introduces multiple casts (to go from the bilge bitfield type to e.g u16 to u64) and more importantly it breaks the migration stream because the Rust vmstate macros are not yet type safe. So, just make everything 32-bits wide. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2024-12-19 19:36:38 +01:00
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hw	rust: pl011: extend registers to 32 bits	2024-12-19 19:36:38 +01:00
qemu-api	rust: qemu-api: add a module to wrap functions and zero-sized closures	2024-12-19 19:36:37 +01:00
qemu-api-macros	rust: rename qemu-api modules to follow C code a bit more	2024-12-19 19:36:37 +01:00
.gitignore	rust: add bindgen step as a meson dependency	2024-10-11 12:32:17 +02:00
Cargo.lock	rust: introduce alternative implementation of offset_of!	2024-11-05 14:18:16 +01:00
Cargo.toml	rust: qom: add casting functionality	2024-12-19 19:36:37 +01:00
Kconfig	rust: add PL011 device model	2024-11-05 14:18:15 +01:00
meson.build	rust: build: add "make clippy", "make rustfmt", "make rustdoc"	2024-12-10 18:44:06 +01:00
rustfmt.toml	rust: add crate to expose bindings and interfaces	2024-10-11 12:32:17 +02:00
wrapper.h	rust/wrapper.h: define memory_order enum	2024-11-05 14:18:15 +01:00