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https://github.com/Motorhead1991/qemu.git
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9d7a951e35
MSI interrupt is triggered by writing message on specified memory address. In generic it is used by PCI devices, and no device is connected pch MSI irqchip with GPIO pin line method, here remove gpio input setting for MSI controller. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250410085004.3577627-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU Loongson 7A1000 msi interrupt controller.
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/intc/loongarch_pch_msi.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "hw/pci/msi.h"
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#include "hw/misc/unimp.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
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int irq_num;
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/*
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* vector number is irq number from upper extioi intc
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* need subtract irq base to get msi vector offset
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*/
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irq_num = (val & 0xff) - s->irq_base;
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trace_loongarch_msi_set_irq(irq_num);
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assert(irq_num < s->irq_num);
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qemu_set_irq(s->pch_msi_irq[irq_num], 1);
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}
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static const MemoryRegionOps loongarch_pch_msi_ops = {
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.read = loongarch_msi_mem_read,
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.write = loongarch_msi_mem_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
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if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
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error_setg(errp, "Invalid 'msi_irq_num'");
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return;
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}
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s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
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qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
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}
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static void loongarch_pch_msi_unrealize(DeviceState *dev)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
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g_free(s->pch_msi_irq);
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}
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static void loongarch_pch_msi_init(Object *obj)
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{
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LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
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s, TYPE_LOONGARCH_PCH_MSI, 0x8);
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sysbus_init_mmio(sbd, &s->msi_mmio);
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msi_nonbroken = true;
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}
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static const Property loongarch_msi_properties[] = {
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DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
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DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
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};
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static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = loongarch_pch_msi_realize;
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dc->unrealize = loongarch_pch_msi_unrealize;
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device_class_set_props(dc, loongarch_msi_properties);
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}
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static const TypeInfo loongarch_pch_msi_info = {
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.name = TYPE_LOONGARCH_PCH_MSI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LoongArchPCHMSI),
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.instance_init = loongarch_pch_msi_init,
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.class_init = loongarch_pch_msi_class_init,
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};
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static void loongarch_pch_msi_register_types(void)
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{
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type_register_static(&loongarch_pch_msi_info);
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}
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type_init(loongarch_pch_msi_register_types)
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