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e13c7d3b5b
This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Max Chou <max.chou@sifive.com> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> [max.chou@sifive.com: Exposed x-zvbc property] Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* RISC-V Vector Crypto Extension Helpers for QEMU.
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*
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* Copyright (C) 2023 SiFive, Inc.
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* Written by Codethink Ltd and SiFive.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "qemu/bitops.h"
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#include "cpu.h"
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#include "exec/memop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "internals.h"
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#include "vector_internals.h"
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static uint64_t clmul64(uint64_t y, uint64_t x)
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{
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uint64_t result = 0;
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for (int j = 63; j >= 0; j--) {
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if ((y >> j) & 1) {
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result ^= (x << j);
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}
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}
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return result;
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}
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static uint64_t clmulh64(uint64_t y, uint64_t x)
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{
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uint64_t result = 0;
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for (int j = 63; j >= 1; j--) {
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if ((y >> j) & 1) {
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result ^= (x >> (64 - j));
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}
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}
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return result;
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}
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RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64)
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GEN_VEXT_VV(vclmul_vv, 8)
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RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64)
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GEN_VEXT_VX(vclmul_vx, 8)
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RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64)
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GEN_VEXT_VV(vclmulh_vv, 8)
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RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64)
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GEN_VEXT_VX(vclmulh_vx, 8)
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