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e0c87e3067
The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode APLIC controller. Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This attribute represents the base configuration address for MSIs, in our case the base addr of the IMSIC controller. This attribute is being set only when running irqchip_split() mode with aia=aplic-imsic. During riscv_aplic_msi_send() we'll check if the attribute was set to skip the check for a m-mode APLIC controller and to change the resulting MSI addr by adding kvm_msicfgaddr right before address_space_stl_le(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic.h | ||
| arm_gic_common.h | ||
| arm_gicv3.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| armv7m_nvic.h | ||
| aspeed_intc.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| exynos4210_combiner.h | ||
| exynos4210_gic.h | ||
| goldfish_pic.h | ||
| grlib_irqmp.h | ||
| heathrow_pic.h | ||
| i8259.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| ioapic.h | ||
| kvm_irqcount.h | ||
| loongarch_extioi.h | ||
| loongarch_ipi.h | ||
| loongarch_pch_msi.h | ||
| loongarch_pch_pic.h | ||
| loongson_ipi.h | ||
| loongson_ipi_common.h | ||
| loongson_liointc.h | ||
| m68k_irqc.h | ||
| mips_gic.h | ||
| ppc-uic.h | ||
| realview_gic.h | ||
| riscv_aclint.h | ||
| riscv_aplic.h | ||
| riscv_imsic.h | ||
| rx_icu.h | ||
| sifive_plic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||