Wilfred Mallawa 0df470c388 riscv: opentitan: fixup plic stride len ... The following change was made to rectify incorrectly set stride length on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was discovered whilst attempting to fix a bug where a timer_interrupt was not serviced on TockOS-OpenTitan. [1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/ Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-21 15:52:56 +10:00
..
boot.c	hw/riscv: Use load address rather than entry point for fw_dynamic next_addr	2021-12-20 14:53:31 +10:00
Kconfig	hw/intc: Rename sifive_clint sources to riscv_aclint sources	2021-09-21 07:56:49 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/riscv: Use error_fatal for SoC realisation	2022-01-08 15:46:09 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	riscv: opentitan: fixup plic stride len	2022-01-21 15:52:56 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id	2021-10-22 23:35:47 +10:00
sifive_e.c	hw/riscv: Use error_fatal for SoC realisation	2022-01-08 15:46:09 +10:00
sifive_u.c	hw/riscv: Use error_fatal for SoC realisation	2022-01-08 15:46:09 +10:00
spike.c	hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id	2021-10-22 23:35:47 +10:00
virt.c	hw/riscv: virt: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00