qemu/target/riscv/insn_trans
Philipp Tomsich dd98a74034 target/riscv: Remove the W-form instructions from Zbs
Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
instructions for Zbs (single-bit instructions).  Remove them.

Note that these instructions had already been removed for the 0.93
version of the draft-B extention and have not been present in the
binutils patches circulating in January 2021.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-07 08:33:05 +10:00
..
trans_privileged.c.inc riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
trans_rva.c.inc target/riscv: Use {get,dest}_gpr for RVA 2021-09-01 11:59:12 +10:00
trans_rvb.c.inc target/riscv: Remove the W-form instructions from Zbs 2021-10-07 08:33:05 +10:00
trans_rvd.c.inc target/riscv: Use {get,dest}_gpr for RVD 2021-09-01 11:59:12 +10:00
trans_rvf.c.inc target/riscv: Use {get,dest}_gpr for RVF 2021-09-01 11:59:12 +10:00
trans_rvh.c.inc target/riscv: Tidy trans_rvh.c.inc 2021-09-01 11:59:12 +10:00
trans_rvi.c.inc target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
trans_rvm.c.inc target/riscv: Move gen_* helpers for RVM 2021-09-01 11:59:12 +10:00
trans_rvv.c.inc target/riscv: Use {get,dest}_gpr for RVV 2021-09-01 11:59:12 +10:00