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Add the necessary files to add a simple RCC implementation with just reads from and writes to registers. Also instantiate the RCC in the STM32L4x5_SoC. It is needed for accurate emulation of all the SoC clocks and timers. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-2-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
/*
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* STM32L4X5 RCC (Reset and clock control)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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*
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* Inspired by the BCM2835 CPRMAN clock manager by Luc Michel.
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*/
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#ifndef HW_STM32L4X5_RCC_H
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#define HW_STM32L4X5_RCC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_STM32L4X5_RCC "stm32l4x5-rcc"
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OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC)
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/* In the Stm32l4x5 clock tree, mux have at most 7 sources */
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#define RCC_NUM_CLOCK_MUX_SRC 7
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struct Stm32l4x5RccState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t cr;
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uint32_t icscr;
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uint32_t cfgr;
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uint32_t pllcfgr;
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uint32_t pllsai1cfgr;
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uint32_t pllsai2cfgr;
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uint32_t cier;
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uint32_t cifr;
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uint32_t ahb1rstr;
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uint32_t ahb2rstr;
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uint32_t ahb3rstr;
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uint32_t apb1rstr1;
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uint32_t apb1rstr2;
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uint32_t apb2rstr;
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uint32_t ahb1enr;
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uint32_t ahb2enr;
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uint32_t ahb3enr;
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uint32_t apb1enr1;
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uint32_t apb1enr2;
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uint32_t apb2enr;
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uint32_t ahb1smenr;
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uint32_t ahb2smenr;
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uint32_t ahb3smenr;
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uint32_t apb1smenr1;
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uint32_t apb1smenr2;
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uint32_t apb2smenr;
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uint32_t ccipr;
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uint32_t bdcr;
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uint32_t csr;
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/* Clock sources */
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Clock *gnd;
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Clock *hsi16_rc;
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Clock *msi_rc;
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Clock *hse;
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Clock *lsi_rc;
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Clock *lse_crystal;
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Clock *sai1_extclk;
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Clock *sai2_extclk;
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qemu_irq irq;
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uint64_t hse_frequency;
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uint64_t sai1_extclk_frequency;
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uint64_t sai2_extclk_frequency;
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};
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#endif /* HW_STM32L4X5_RCC_H */
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