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d59d83a1c3
The old implementation replaces two insns, swapping between b <dest> nop br x30 and adrp x30, <dest> addi x30, x30, lo12:<dest> br x30 There is a race condition in which a thread could be stopped at the PC of the second insn, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b <dest> br tmp and ldr tmp, <jmp_addr> br tmp Reported-by: hev <r@hev.cc> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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| aarch64 | ||
| arm | ||
| i386 | ||
| loongarch64 | ||
| mips | ||
| ppc | ||
| riscv | ||
| s390x | ||
| sparc64 | ||
| tci | ||
| meson.build | ||
| optimize.c | ||
| region.c | ||
| tcg-common.c | ||
| tcg-internal.h | ||
| tcg-ldst.c.inc | ||
| tcg-op-gvec.c | ||
| tcg-op-vec.c | ||
| tcg-op.c | ||
| tcg-pool.c.inc | ||
| tcg.c | ||
| tci.c | ||