qemu/target/riscv/insn_trans
Daniel Henrique Barboza d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.

Call it just once in the end like other functions are doing.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240314175704.478276-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-22 15:23:08 +10:00
..
trans_privileged.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rva.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv: remove 'over' brconds from vector trans 2024-03-22 15:21:35 +10:00
trans_rvd.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvf.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvi.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc trans_rvv.c.inc: remove redundant mark_vs_dirty() calls 2024-03-22 15:23:08 +10:00
trans_rvvk.c.inc target/riscv: remove 'over' brconds from vector trans 2024-03-22 15:21:35 +10:00
trans_rvzacas.c.inc target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Update $ra with current $pc in trans_cm_jalt() 2024-03-08 15:37:20 +10:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc target/riscv: rename ext_icboz to ext_zicboz 2023-11-07 11:02:17 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_xthead.c.inc target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00