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The architectural feature RASv1p1 introduces the following new features: * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 * new bits in the fine-grained trap registers that control traps for these new registers * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 * a larger number of the ERXMISC<n>_EL1 registers * the format of ERR<n>STATUS registers changes The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN and SCR_EL3.FIEN bits may be RES0. We don't have any ERR<n>STATUS registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet implement the fine-grained-trap extension. So there is nothing we need to implement to be compliant with the feature spec. Make the 'max' CPU report the feature in its ID registers, and document it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220531114258.855804-1-peter.maydell@linaro.org |
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| .. | ||
| aspeed.rst | ||
| collie.rst | ||
| cpu-features.rst | ||
| cubieboard.rst | ||
| digic.rst | ||
| emcraft-sf2.rst | ||
| emulation.rst | ||
| gumstix.rst | ||
| highbank.rst | ||
| imx25-pdk.rst | ||
| integratorcp.rst | ||
| kzm.rst | ||
| mainstone.rst | ||
| mps2.rst | ||
| musca.rst | ||
| musicpal.rst | ||
| nrf.rst | ||
| nseries.rst | ||
| nuvoton.rst | ||
| orangepi.rst | ||
| palm.rst | ||
| raspi.rst | ||
| realview.rst | ||
| sabrelite.rst | ||
| sbsa.rst | ||
| stellaris.rst | ||
| stm32.rst | ||
| sx1.rst | ||
| versatile.rst | ||
| vexpress.rst | ||
| virt.rst | ||
| xlnx-versal-virt.rst | ||
| xscale.rst | ||