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404e75343c
It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change in AST2700. Each GPIO pin has their own control register. In other words, users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and use it in aspeed_gpio_realize function. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/*
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* ASPEED GPIO Controller
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*
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* Copyright (C) 2017-2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_GPIO_H
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#define ASPEED_GPIO_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_GPIO "aspeed.gpio"
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OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO)
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#define ASPEED_GPIO_MAX_NR_SETS 8
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#define ASPEED_GPIOS_PER_SET 32
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#define ASPEED_REGS_PER_BANK 14
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#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
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#define ASPEED_GROUPS_PER_SET 4
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#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
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#define ASPEED_CHARS_PER_GROUP_LABEL 4
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typedef struct GPIOSets GPIOSets;
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typedef struct GPIOSetProperties {
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uint32_t input;
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uint32_t output;
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char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
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} GPIOSetProperties;
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enum GPIORegType {
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gpio_not_a_reg,
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gpio_reg_data_value,
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gpio_reg_direction,
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gpio_reg_int_enable,
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gpio_reg_int_sens_0,
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gpio_reg_int_sens_1,
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gpio_reg_int_sens_2,
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gpio_reg_int_status,
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gpio_reg_reset_tolerant,
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gpio_reg_debounce_1,
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gpio_reg_debounce_2,
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gpio_reg_cmd_source_0,
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gpio_reg_cmd_source_1,
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gpio_reg_data_read,
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gpio_reg_input_mask,
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};
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/* GPIO index mode */
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enum GPIORegIndexType {
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gpio_reg_idx_data = 0,
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gpio_reg_idx_direction,
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gpio_reg_idx_interrupt,
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gpio_reg_idx_debounce,
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gpio_reg_idx_tolerance,
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gpio_reg_idx_cmd_src,
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gpio_reg_idx_input_mask,
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gpio_reg_idx_reserved,
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gpio_reg_idx_new_w_cmd_src,
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gpio_reg_idx_new_r_cmd_src,
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};
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typedef struct AspeedGPIOReg {
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uint16_t set_idx;
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enum GPIORegType type;
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} AspeedGPIOReg;
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struct AspeedGPIOClass {
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SysBusDevice parent_obj;
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const GPIOSetProperties *props;
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uint32_t nr_gpio_pins;
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uint32_t nr_gpio_sets;
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const AspeedGPIOReg *reg_table;
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unsigned reg_table_count;
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uint64_t mem_size;
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const MemoryRegionOps *reg_ops;
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};
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struct AspeedGPIOState {
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/* <private> */
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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int pending;
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qemu_irq irq;
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qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET];
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/* Parallel GPIO Registers */
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uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
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struct GPIOSets {
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uint32_t data_value; /* Reflects pin values */
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uint32_t data_read; /* Contains last value written to data value */
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uint32_t direction;
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uint32_t int_enable;
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uint32_t int_sens_0;
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uint32_t int_sens_1;
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uint32_t int_sens_2;
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uint32_t int_status;
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uint32_t reset_tol;
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uint32_t cmd_source_0;
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uint32_t cmd_source_1;
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uint32_t debounce_1;
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uint32_t debounce_2;
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uint32_t input_mask;
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} sets[ASPEED_GPIO_MAX_NR_SETS];
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};
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#endif /* ASPEED_GPIO_H */
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