qemu/docs/system
Yu Li 7035b8420f docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16 12:25:52 +10:00
..
arm
devices
i386
ppc
riscv docs/system: riscv: Update description of CPU 2022-02-16 12:25:52 +10:00
s390x
authz.rst
barrier.rst
bootindex.rst
confidential-guest-support.rst
cpu-hotplug.rst
cpu-models-mips.rst.inc
cpu-models-x86-abi.csv
cpu-models-x86.rst.inc
device-emulation.rst
device-url-syntax.rst.inc
gdb.rst
generic-loader.rst
guest-loader.rst
images.rst
index.rst
invocation.rst
keys.rst
keys.rst.inc
linuxboot.rst
managed-startup.rst
monitor.rst
multi-process.rst
mux-chardev.rst
mux-chardev.rst.inc
pr-manager.rst
qemu-block-drivers.rst
qemu-block-drivers.rst.inc
qemu-cpu-models.rst
qemu-manpage.rst
quickstart.rst
secrets.rst
security.rst
target-arm.rst
target-avr.rst
target-i386-desc.rst.inc
target-i386.rst
target-m68k.rst
target-mips.rst
target-ppc.rst
target-riscv.rst
target-rx.rst
target-s390x.rst
target-sparc.rst
target-sparc64.rst
target-xtensa.rst
targets.rst
tls.rst
virtio-net-failover.rst
vnc-security.rst