mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-12-24 00:18:36 -07:00
cf04aba2a9
A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of as a PCIe device with extra functionality when enumerated and enabled. For this reason, CXL does here, and will continue to add on to existing PCI code paths. Host bridges will typically need to be handled specially and so they can implement this newly introduced interface or not. All other components should implement this interface. Implementing this interface allows the core PCI code to treat these devices as special where appropriate. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Adam Manzanares <a.manzanares@samsung.com> Message-Id: <20220429144110.25167-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
||
|---|---|---|
| .. | ||
| msi.h | ||
| msix.h | ||
| pci.h | ||
| pci_bridge.h | ||
| pci_bus.h | ||
| pci_host.h | ||
| pci_ids.h | ||
| pci_regs.h | ||
| pcie.h | ||
| pcie_aer.h | ||
| pcie_host.h | ||
| pcie_port.h | ||
| pcie_regs.h | ||
| pcie_sriov.h | ||
| shpc.h | ||
| slotid_cap.h | ||