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cb135f59b8
This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
392 lines
12 KiB
C
392 lines
12 KiB
C
/*
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* ioapic.c IOAPIC emulation logic
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* Split the ioapic logic from apic.c
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "monitor/monitor.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/ioapic.h"
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#include "hw/i386/ioapic_internal.h"
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#include "include/hw/pci/msi.h"
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#include "sysemu/kvm.h"
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#include "target-i386/cpu.h"
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#include "hw/i386/apic-msidef.h"
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//#define DEBUG_IOAPIC
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#ifdef DEBUG_IOAPIC
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#define DPRINTF(fmt, ...) \
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do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define APIC_DELIVERY_MODE_SHIFT 8
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#define APIC_POLARITY_SHIFT 14
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#define APIC_TRIG_MODE_SHIFT 15
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static IOAPICCommonState *ioapics[MAX_IOAPICS];
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/* global variable from ioapic_common.c */
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extern int ioapic_no;
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static void ioapic_service(IOAPICCommonState *s)
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{
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AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
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uint32_t addr, data;
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uint8_t i;
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uint8_t trig_mode;
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uint8_t vector;
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uint8_t delivery_mode;
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uint32_t mask;
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uint64_t entry;
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uint16_t dest_idx;
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uint8_t dest_mode;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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mask = 1 << i;
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if (s->irr & mask) {
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int coalesce = 0;
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entry = s->ioredtbl[i];
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if (!(entry & IOAPIC_LVT_MASKED)) {
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trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
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/*
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* By default, this would be dest_id[8] +
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* reserved[8]. When IR is enabled, this would be
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* interrupt_index[15] + interrupt_format[1]. This
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* field never means anything, but only used to
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* generate corresponding MSI.
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*/
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dest_idx = entry >> IOAPIC_LVT_DEST_IDX_SHIFT;
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dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
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delivery_mode =
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(entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
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if (trig_mode == IOAPIC_TRIGGER_EDGE) {
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s->irr &= ~mask;
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} else {
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coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
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s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
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}
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if (delivery_mode == IOAPIC_DM_EXTINT) {
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vector = pic_read_irq(isa_pic);
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} else {
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vector = entry & IOAPIC_VECTOR_MASK;
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}
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#ifdef CONFIG_KVM
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if (kvm_irqchip_is_split()) {
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if (trig_mode == IOAPIC_TRIGGER_EDGE) {
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kvm_set_irq(kvm_state, i, 1);
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kvm_set_irq(kvm_state, i, 0);
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} else {
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if (!coalesce) {
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kvm_set_irq(kvm_state, i, 1);
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}
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}
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continue;
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}
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#else
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(void)coalesce;
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#endif
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/* No matter whether IR is enabled, we translate
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* the IOAPIC message into a MSI one, and its
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* address space will decide whether we need a
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* translation. */
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addr = APIC_DEFAULT_ADDRESS | \
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(dest_idx << MSI_ADDR_DEST_IDX_SHIFT) |
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(dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
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data = (vector << MSI_DATA_VECTOR_SHIFT) |
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(trig_mode << MSI_DATA_TRIGGER_SHIFT) |
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(delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
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stl_le_phys(ioapic_as, addr, data);
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}
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}
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}
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}
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static void ioapic_set_irq(void *opaque, int vector, int level)
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{
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IOAPICCommonState *s = opaque;
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/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
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if (vector == 0) {
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vector = 2;
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}
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if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
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uint32_t mask = 1 << vector;
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uint64_t entry = s->ioredtbl[vector];
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if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
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IOAPIC_TRIGGER_LEVEL) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
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ioapic_service(s);
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}
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} else {
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s->irr &= ~mask;
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}
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} else {
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/* According to the 82093AA manual, we must ignore edge requests
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* if the input pin is masked. */
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if (level && !(entry & IOAPIC_LVT_MASKED)) {
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s->irr |= mask;
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ioapic_service(s);
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}
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}
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}
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}
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static void ioapic_update_kvm_routes(IOAPICCommonState *s)
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{
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#ifdef CONFIG_KVM
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int i;
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if (kvm_irqchip_is_split()) {
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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uint64_t entry = s->ioredtbl[i];
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uint8_t trig_mode;
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uint8_t delivery_mode;
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uint8_t dest;
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uint8_t dest_mode;
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uint64_t pin_polarity;
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MSIMessage msg;
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trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
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dest = entry >> IOAPIC_LVT_DEST_SHIFT;
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dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
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pin_polarity = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
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delivery_mode =
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(entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
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msg.address = APIC_DEFAULT_ADDRESS;
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msg.address |= dest_mode << 2;
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msg.address |= dest << 12;
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msg.data = entry & IOAPIC_VECTOR_MASK;
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msg.data |= delivery_mode << APIC_DELIVERY_MODE_SHIFT;
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msg.data |= pin_polarity << APIC_POLARITY_SHIFT;
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msg.data |= trig_mode << APIC_TRIG_MODE_SHIFT;
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kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
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}
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kvm_irqchip_commit_routes(kvm_state);
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}
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#endif
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}
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void ioapic_eoi_broadcast(int vector)
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{
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IOAPICCommonState *s;
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uint64_t entry;
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int i, n;
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for (i = 0; i < MAX_IOAPICS; i++) {
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s = ioapics[i];
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if (!s) {
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continue;
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}
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for (n = 0; n < IOAPIC_NUM_PINS; n++) {
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entry = s->ioredtbl[n];
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if ((entry & IOAPIC_LVT_REMOTE_IRR)
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&& (entry & IOAPIC_VECTOR_MASK) == vector) {
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s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
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if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
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ioapic_service(s);
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}
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}
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}
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}
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}
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void ioapic_dump_state(Monitor *mon, const QDict *qdict)
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{
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int i;
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for (i = 0; i < MAX_IOAPICS; i++) {
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if (ioapics[i] != 0) {
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ioapic_print_redtbl(mon, ioapics[i]);
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}
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}
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}
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static uint64_t
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ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
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{
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IOAPICCommonState *s = opaque;
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int index;
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uint32_t val = 0;
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switch (addr & 0xff) {
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case IOAPIC_IOREGSEL:
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val = s->ioregsel;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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case IOAPIC_REG_ARB:
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val = s->id << IOAPIC_ID_SHIFT;
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break;
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case IOAPIC_REG_VER:
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val = IOAPIC_VERSION |
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((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1) {
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val = s->ioredtbl[index] >> 32;
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} else {
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val = s->ioredtbl[index] & 0xffffffff;
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}
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}
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}
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DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
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break;
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}
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return val;
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}
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/*
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* This is to satisfy the hack in Linux kernel. One hack of it is to
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* simulate clearing the Remote IRR bit of IOAPIC entry using the
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* following:
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*
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* "For IO-APIC's with EOI register, we use that to do an explicit EOI.
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* Otherwise, we simulate the EOI message manually by changing the trigger
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* mode to edge and then back to level, with RTE being masked during
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* this."
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*
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* (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
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*
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* This is based on the assumption that, Remote IRR bit will be
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* cleared by IOAPIC hardware when configured as edge-triggered
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* interrupts.
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*
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* Without this, level-triggered interrupts in IR mode might fail to
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* work correctly.
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*/
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static inline void
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ioapic_fix_edge_remote_irr(uint64_t *entry)
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{
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if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
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/* Edge-triggered interrupts, make sure remote IRR is zero */
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*entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
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}
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}
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static void
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ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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IOAPICCommonState *s = opaque;
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int index;
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switch (addr & 0xff) {
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case IOAPIC_IOREGSEL:
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s->ioregsel = val;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
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break;
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case IOAPIC_REG_VER:
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case IOAPIC_REG_ARB:
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
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if (s->ioregsel & 1) {
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s->ioredtbl[index] &= 0xffffffff;
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s->ioredtbl[index] |= (uint64_t)val << 32;
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} else {
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s->ioredtbl[index] &= ~0xffffffffULL;
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s->ioredtbl[index] |= val;
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}
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/* restore RO bits */
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s->ioredtbl[index] &= IOAPIC_RW_BITS;
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s->ioredtbl[index] |= ro_bits;
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ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
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ioapic_service(s);
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}
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}
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break;
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}
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ioapic_update_kvm_routes(s);
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}
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static const MemoryRegionOps ioapic_io_ops = {
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.read = ioapic_mem_read,
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.write = ioapic_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ioapic_realize(DeviceState *dev, Error **errp)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
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"ioapic", 0x1000);
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qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
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ioapics[ioapic_no] = s;
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}
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static void ioapic_class_init(ObjectClass *klass, void *data)
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{
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IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = ioapic_realize;
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dc->reset = ioapic_reset_common;
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}
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static const TypeInfo ioapic_info = {
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.name = "ioapic",
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.parent = TYPE_IOAPIC_COMMON,
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.instance_size = sizeof(IOAPICCommonState),
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.class_init = ioapic_class_init,
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};
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static void ioapic_register_types(void)
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{
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type_register_static(&ioapic_info);
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}
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type_init(ioapic_register_types)
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