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c6e07f03f7
The LPC HC irq status register bits are set when an LPC IRQSER input is asserted. These irq status bits drive the PSI irq to the CPU interrupt controller. The LPC HC irq status bits are cleared by software writing to the register with 1's for the bits to clear. Existing register write was clearing the irq status bits even when the input was asserted, this results in interrupts being lost. This fix changes the behavior to keep track of the device IRQ status in internal state that is separate from the irq status register, and only allowing the irq status bits to be cleared if the associated input is not asserted. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> [np: rebased before P9 PSI SERIRQ patch, adjust changelog/comments] Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> |
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| authz | ||
| block | ||
| chardev | ||
| crypto | ||
| disas | ||
| exec | ||
| fpu | ||
| gdbstub | ||
| hw | ||
| io | ||
| libdecnumber | ||
| migration | ||
| monitor | ||
| net | ||
| qapi | ||
| qemu | ||
| qom | ||
| scsi | ||
| semihosting | ||
| standard-headers | ||
| sysemu | ||
| tcg | ||
| ui | ||
| user | ||
| elf.h | ||
| glib-compat.h | ||
| qemu-io.h | ||
| qemu-main.h | ||