Akihiko Odaki bedcc7465d target/arm: Define raw write for PMU CLR registers ... Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their default write function, which clears written bits instead of writes the raw value. PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead had ARM_CP_NO_RAW. Commit 7a0e58fa64 ("target-arm: Split NO_MIGRATE into ALIAS and NO_RAW") sugguests ARM_CP_ALIAS should be used instead of ARM_CP_NO_RAW in such a case: > We currently mark ARM coprocessor/system register definitions with > the flag ARM_CP_NO_MIGRATE for two different reasons: > 1) register is an alias on to state that's also visible via > some other register, and that other register is the one > responsible for migrating the state > 2) register is not actually state at all (for instance the TLB > or cache maintenance operation "registers") and it makes no > sense to attempt to migrate it or otherwise access the raw state > > This works fine for identifying which registers should be ignored > when performing migration, but we also use the same functions for > synchronizing system register state between QEMU and the kernel > when using KVM. In this case we don't want to try to sync state > into registers in category 2, but we do want to sync into registers > in category 1, because the kernel might have picked a different > one of the aliases as its choice for which one to expose for > migration. These registers fall in category 1 (ARM_CP_ALIAS), not category 2 (ARM_CP_NO_RAW). ARM_CP_NO_RAW also has another undesired side effect that hides registers from GDB. Properly set raw write functions and drop the ARM_CP_NO_RAW flag from PMINTENCLR and PMINTENCLR_EL1; this fixes GDB/KVM state synchronization of PMCNTENCLR and PMCNTENCLR_EL0, and exposes all these four registers to GDB. It is not necessary to add ARM_CP_ALIAS to these registers because the flag is already set. Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Message-id: 20250531-clr-v3-1-377f9bf1746d@rsg.ci.i.u-tokyo.ac.jp Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2025-06-13 11:03:20 +01:00
..
alpha	target: Use cpu_pointer_wrap_notreached for strict align targets	2025-05-28 08:08:47 +01:00
arm	target/arm: Define raw write for PMU CLR registers	2025-06-13 11:03:20 +01:00
avr	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
hexagon	accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps	2025-04-30 12:45:05 -07:00
hppa	target: Use cpu_pointer_wrap_notreached for strict align targets	2025-05-28 08:08:47 +01:00
i386	hw/core/cpu: Move CacheType to general cpu.h	2025-06-10 12:59:09 +02:00
loongarch	target/loongarch: add check for fcond	2025-06-10 15:00:14 +08:00
m68k	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
microblaze	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
mips	* target/i386/kvm: Intel TDX support	2025-05-30 11:41:07 -04:00
openrisc	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
ppc	* target/i386/kvm: Intel TDX support	2025-05-30 11:41:07 -04:00
riscv	* target/i386/kvm: Intel TDX support	2025-05-30 11:41:07 -04:00
rx	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
s390x	vfio queue:	2025-06-11 11:39:53 -04:00
sh4	target: Use cpu_pointer_wrap_notreached for strict align targets	2025-05-28 08:08:47 +01:00
sparc	accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW	2025-05-28 15:17:25 -04:00
tricore	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
xtensa	target: Use cpu_pointer_wrap_uint32 for 32-bit targets	2025-05-28 08:08:48 +01:00
Kconfig	target/cris: Remove the deprecated CRIS target	2024-09-13 20:11:13 +02:00
meson.build	target/cris: Remove the deprecated CRIS target	2024-09-13 20:11:13 +02:00