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The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231121144605.3980419-1-peter.maydell@linaro.org |
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