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c3513c836e
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
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|---|---|---|
| .. | ||
| cpu.c | ||
| cpu.h | ||
| exception.c | ||
| exception.h | ||
| exception_helper.c | ||
| fpu_helper.c | ||
| gdbstub.c | ||
| helper.h | ||
| insns.decode | ||
| interrupt.c | ||
| interrupt_helper.c | ||
| machine.c | ||
| Makefile.objs | ||
| mmu.c | ||
| mmu_helper.c | ||
| sys_helper.c | ||
| translate.c | ||