Fabien Chouteau 30efbf330a SiFive RISC-V GPIO Device ... QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-24 11:58:30 -07:00
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Kconfig	kconfig: add CONFIG_MSI_NONBROKEN	2019-03-18 09:39:57 +01:00
Makefile.objs	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Fix CLINT timecmp low 32-bit writes	2018-12-20 12:08:43 -08:00
sifive_e.c	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_gpio.c	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_plic.c	riscv: plic: Log guest errors	2019-04-04 16:36:21 -07:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	riscv: sifive_u: Correct UART0's IRQ in the device tree	2019-03-19 05:18:42 -07:00
sifive_uart.c	riscv: sifive_uart: Generate TX interrupt	2019-03-19 05:18:28 -07:00
spike.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
virt.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00