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b0a1009192
The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchdog/programmers-model The new tests have to target an MPS2 machine because the original machine used by the test (stellaris) has a variation of the cmsdk_apb_watchdog that locks INTEN when it is programmed to 1. The stellaris machine also does not reproduce the problem of the counter running out of cold reset due to the way the clocks are initialized. Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com> Reviewed-by: Stephen Longfield <slongfield@google.com> Message-id: 20241115160328.1650269-6-roqueh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
399 lines
14 KiB
C
399 lines
14 KiB
C
/*
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* QTest testcase for the CMSDK APB watchdog device
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*
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* Copyright (c) 2021 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "exec/hwaddr.h"
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#include "qemu/bitops.h"
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#include "libqtest-single.h"
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#define WDOG_BASE 0x40000000
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#define WDOG_BASE_MPS2 0x40008000
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#define WDOGLOAD 0
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#define WDOGVALUE 4
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#define WDOGCONTROL 8
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#define WDOGINTCLR 0xc
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#define WDOGRIS 0x10
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#define WDOGMIS 0x14
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#define WDOGLOCK 0xc00
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#define SSYS_BASE 0x400fe000
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#define RCC 0x60
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#define SYSDIV_SHIFT 23
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#define SYSDIV_LENGTH 4
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#define WDOGLOAD_DEFAULT 0xFFFFFFFF
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#define WDOGVALUE_DEFAULT 0xFFFFFFFF
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typedef struct CMSDKAPBWatchdogTestArgs {
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int64_t tick;
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hwaddr wdog_base;
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const char *machine;
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} CMSDKAPBWatchdogTestArgs;
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enum {
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MACHINE_LM3S811EVB,
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MACHINE_MPS2_AN385,
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};
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/*
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* lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
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* which is 80ns per tick.
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*
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* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick
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*/
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static const CMSDKAPBWatchdogTestArgs machine_info[] = {
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[MACHINE_LM3S811EVB] = {
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.tick = 80,
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.wdog_base = WDOG_BASE,
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.machine = "lm3s811evb",
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},
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[MACHINE_MPS2_AN385] = {
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.tick = 40,
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.wdog_base = WDOG_BASE_MPS2,
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.machine = "mps2-an385",
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},
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};
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static void system_reset(QTestState *qtest)
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{
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QDict *resp;
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resp = qtest_qmp(qtest, "{'execute': 'system_reset'}");
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g_assert(qdict_haskey(resp, "return"));
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qobject_unref(resp);
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qtest_qmp_eventwait(qtest, "RESET");
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}
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static void test_watchdog(const void *ptr)
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{
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const CMSDKAPBWatchdogTestArgs *args = ptr;
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hwaddr wdog_base = args->wdog_base;
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int64_t tick = args->tick;
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g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine);
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qtest_start(cmdline);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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writel(wdog_base + WDOGCONTROL, 1);
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writel(wdog_base + WDOGLOAD, 1000);
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/* Step to just past the 500th tick */
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clock_step(500 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 500);
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/* Just past the 1000th tick: timer should have fired */
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clock_step(500 * tick);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 1);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 0);
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/* VALUE reloads at following tick */
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clock_step(tick);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000);
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/* Writing any value to WDOGINTCLR clears the interrupt and reloads */
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clock_step(500 * tick);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 500);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 1);
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writel(wdog_base + WDOGINTCLR, 0);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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qtest_end();
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}
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/*
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* This test can only be executed in the stellaris board since it relies on a
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* component of the board to change the clocking parameters of the watchdog.
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*/
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static void test_clock_change(const void *ptr)
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{
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uint32_t rcc;
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const CMSDKAPBWatchdogTestArgs *args = ptr;
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g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine);
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qtest_start(cmdline);
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/*
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* Test that writing to the stellaris board's RCC register to
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* change the system clock frequency causes the watchdog
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* to change the speed it counts at.
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*/
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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writel(WDOG_BASE + WDOGCONTROL, 1);
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writel(WDOG_BASE + WDOGLOAD, 1000);
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/* Step to just past the 500th tick */
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clock_step(80 * 500 + 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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/* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
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rcc = readl(SSYS_BASE + RCC);
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g_assert_cmphex(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
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rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
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writel(SSYS_BASE + RCC, rcc);
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/* Just past the 1000th tick: timer should have fired */
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clock_step(40 * 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
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/* VALUE reloads at following tick */
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clock_step(41);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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/* Writing any value to WDOGINTCLR clears the interrupt and reloads */
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clock_step(40 * 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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writel(WDOG_BASE + WDOGINTCLR, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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qtest_end();
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}
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/* Tests the counter is not running after reset. */
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static void test_watchdog_reset(const void *ptr)
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{
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const CMSDKAPBWatchdogTestArgs *args = ptr;
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hwaddr wdog_base = args->wdog_base;
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int64_t tick = args->tick;
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g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine);
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qtest_start(cmdline);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGCONTROL), ==, 0);
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/*
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* The counter should not be running if WDOGCONTROL.INTEN has not been set,
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* as it is the case after a cold reset.
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*/
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clock_step(15 * tick + 1);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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/* Let the counter run before reset */
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writel(wdog_base + WDOGLOAD, 3000);
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writel(wdog_base + WDOGCONTROL, 1);
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/* Verify it is running */
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clock_step(1000 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 3000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 2000);
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system_reset(global_qtest);
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/* Check defaults after reset */
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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/* The counter should not be running after reset. */
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clock_step(1000 * tick + 1);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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qtest_end();
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}
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/*
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* Tests inten works as the counter enable based on this description:
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*
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* Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and the
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* interrupt, or LOW to disable the counter and interrupt. Reloads the counter
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* from the value in WDOGLOAD when the interrupt is enabled, after previously
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* being disabled.
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*/
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static void test_watchdog_inten(const void *ptr)
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{
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const CMSDKAPBWatchdogTestArgs *args = ptr;
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hwaddr wdog_base = args->wdog_base;
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int64_t tick = args->tick;
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g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine);
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qtest_start(cmdline);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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/*
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* When WDOGLOAD is written to, the count is immediately restarted from the
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* new value.
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*
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* Note: the counter should not be running as long as WDOGCONTROL.INTEN is
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* not set
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*/
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writel(wdog_base + WDOGLOAD, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 4000);
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clock_step(500 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 4000);
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/* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt */
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writel(wdog_base + WDOGCONTROL, 1);
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clock_step(500 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 3500);
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/* or LOW to disable the counter and interrupt. */
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writel(wdog_base + WDOGCONTROL, 0);
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clock_step(100 * tick);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 3500);
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/*
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* Reloads the counter from the value in WDOGLOAD when the interrupt is
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* enabled, after previously being disabled.
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*/
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writel(wdog_base + WDOGCONTROL, 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 4000);
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/* Test counter is still on */
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clock_step(50 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 3950);
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/*
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* When WDOGLOAD is written to, the count is immediately restarted from the
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* new value.
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*
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* Note: the counter should be running since WDOGCONTROL.INTEN is set
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*/
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writel(wdog_base + WDOGLOAD, 5000);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 5000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 5000);
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clock_step(4999 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 5000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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/* Finally disable and check the conditions don't change */
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writel(wdog_base + WDOGCONTROL, 0);
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clock_step(10 * tick);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 5000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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qtest_end();
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}
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/*
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* Tests the following custom behavior:
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*
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* The Luminary version of this device ignores writes to this register after the
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* guest has enabled interrupts (so they can only be disabled again via reset).
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*/
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static void test_watchdog_inten_luminary(const void *ptr)
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{
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const CMSDKAPBWatchdogTestArgs *args = ptr;
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hwaddr wdog_base = args->wdog_base;
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int64_t tick = args->tick;
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g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine);
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qtest_start(cmdline);
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g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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/*
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* When WDOGLOAD is written to, the count is immediately restarted from the
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* new value.
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*
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* Note: the counter should not be running as long as WDOGCONTROL.INTEN is
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* not set
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*/
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writel(wdog_base + WDOGLOAD, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 4000);
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clock_step(500 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 4000);
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/* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt */
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writel(wdog_base + WDOGCONTROL, 1);
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clock_step(500 * tick + 1);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 3500);
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/*
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* The Luminary version of this device ignores writes to this register after
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* the guest has enabled interrupts
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*/
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writel(wdog_base + WDOGCONTROL, 0);
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clock_step(100 * tick);
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g_assert_cmpuint(readl(wdog_base + WDOGLOAD), ==, 4000);
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g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 3400);
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g_assert_cmphex(readl(wdog_base + WDOGCONTROL), ==, 0x1);
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/* They can only be disabled again via reset */
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system_reset(global_qtest);
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/* Check defaults after reset */
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGCONTROL), ==, 0);
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/* The counter should not be running after reset. */
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clock_step(1000 * tick + 1);
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g_assert_cmphex(readl(wdog_base + WDOGLOAD), ==, WDOGLOAD_DEFAULT);
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g_assert_cmphex(readl(wdog_base + WDOGVALUE), ==, WDOGVALUE_DEFAULT);
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qtest_end();
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}
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int main(int argc, char **argv)
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{
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int r;
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g_test_init(&argc, &argv, NULL);
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g_test_set_nonfatal_assertions();
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if (qtest_has_machine(machine_info[MACHINE_LM3S811EVB].machine)) {
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog",
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&machine_info[MACHINE_LM3S811EVB], test_watchdog);
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_clock_change",
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&machine_info[MACHINE_LM3S811EVB],
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test_clock_change);
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset",
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&machine_info[MACHINE_LM3S811EVB],
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test_watchdog_reset);
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten_luminary",
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&machine_info[MACHINE_LM3S811EVB],
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test_watchdog_inten_luminary);
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}
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if (qtest_has_machine(machine_info[MACHINE_MPS2_AN385].machine)) {
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_mps2",
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&machine_info[MACHINE_MPS2_AN385], test_watchdog);
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset_mps2",
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&machine_info[MACHINE_MPS2_AN385],
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test_watchdog_reset);
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qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten",
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&machine_info[MACHINE_MPS2_AN385],
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test_watchdog_inten);
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}
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r = g_test_run();
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return r;
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}
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