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qemu/tcg/riscv
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Roman Artemev b438362a14 tcg/riscv: Fix StoreStore barrier generation 
On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76 ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-12 14:28:38 -06:00
..
tcg-target-con-set.h tcg/riscv: Implement vector shi/s/v ops 2024-10-22 11:57:25 -07:00
tcg-target-con-str.h tcg/riscv: Implement vector cmp/cmpsel ops 2024-10-22 11:57:25 -07:00
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00
tcg-target.c.inc tcg/riscv: Fix StoreStore barrier generation 2024-12-12 14:28:38 -06:00
tcg-target.h tcg/riscv: Enable native vector support for TCG host 2024-10-22 11:57:25 -07:00
tcg-target.opc.h tcg/riscv: Add basic support for vector 2024-10-22 11:57:25 -07:00