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5c3ba81055
Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
/*
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* MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
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*
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* Copyright (c) 2014 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "fpu/softfloat.h"
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#include "fpu_helper.h"
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void msa_reset(CPUMIPSState *env)
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{
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if (!ase_msa_available(env)) {
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return;
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}
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#ifdef CONFIG_USER_ONLY
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/* MSA access enabled */
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env->CP0_Config5 |= 1 << CP0C5_MSAEn;
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env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
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#endif
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/*
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* MSA CSR:
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* - non-signaling floating point exception mode off (NX bit is 0)
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* - Cause, Enables, and Flags are all 0
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* - round to nearest / ties to even (RM bits are 0)
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*/
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env->active_tc.msacsr = 0;
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restore_msa_fp_status(env);
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/* tininess detected after rounding.*/
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set_float_detect_tininess(float_tininess_after_rounding,
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&env->active_tc.msa_fp_status);
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/*
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* According to MIPS specifications, if one of the two operands is
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* a sNaN, a new qNaN has to be generated. This is done in
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* floatXX_silence_nan(). For qNaN inputs the specifications
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* says: "When possible, this QNaN result is one of the operand QNaN
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* values." In practice it seems that most implementations choose
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* the first operand if both operands are qNaN. In short this gives
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* the following rules:
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* 1. A if it is signaling
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* 2. B if it is signaling
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* 3. A (quiet)
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* 4. B (quiet)
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* A signaling NaN is always silenced before returning it.
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*/
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set_float_2nan_prop_rule(float_2nan_prop_s_ab,
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&env->active_tc.msa_fp_status);
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set_float_3nan_prop_rule(float_3nan_prop_s_cab,
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&env->active_tc.msa_fp_status);
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/* clear float_status exception flags */
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set_float_exception_flags(0, &env->active_tc.msa_fp_status);
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/* clear float_status nan mode */
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set_default_nan_mode(0, &env->active_tc.msa_fp_status);
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/* set proper signanling bit meaning ("1" means "quiet") */
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set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
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/* Inf * 0 + NaN returns the input NaN */
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set_float_infzeronan_rule(float_infzeronan_dnan_never,
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&env->active_tc.msa_fp_status);
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/* Default NaN: sign bit clear, frac msb set */
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set_float_default_nan_pattern(0b01000000,
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&env->active_tc.msa_fp_status);
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}
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