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5c3ba81055
Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
107 lines
3.5 KiB
C
107 lines
3.5 KiB
C
/*
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* Helpers for emulation of FPU-related MIPS instructions.
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*
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* Copyright (C) 2004-2005 Jocelyn Mayer
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#include "fpu/softfloat-helpers.h"
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#include "cpu.h"
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extern const FloatRoundMode ieee_rm[4];
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uint32_t float_class_s(uint32_t arg, float_status *fst);
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uint64_t float_class_d(uint64_t arg, float_status *fst);
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static inline void restore_rounding_mode(CPUMIPSState *env)
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{
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set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
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&env->active_fpu.fp_status);
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}
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static inline void restore_flush_mode(CPUMIPSState *env)
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{
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set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
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&env->active_fpu.fp_status);
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}
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static inline void restore_snan_bit_mode(CPUMIPSState *env)
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{
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bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
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FloatInfZeroNaNRule izn_rule;
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Float3NaNPropRule nan3_rule;
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/*
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* With nan2008, SNaNs are silenced in the usual way.
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* Before that, SNaNs are not silenced; default nans are produced.
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*/
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set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
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set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
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/*
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* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
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* case sets InvalidOp and returns the default NaN.
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* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
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* case sets InvalidOp and returns the input value 'c'.
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*/
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izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
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set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
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nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
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set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
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/*
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* With nan2008, the default NaN value has the sign bit clear and the
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* frac msb set; with the older mode, the sign bit is clear, and all
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* frac bits except the msb are set.
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*/
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set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
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&env->active_fpu.fp_status);
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}
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static inline void restore_fp_status(CPUMIPSState *env)
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{
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restore_rounding_mode(env);
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restore_flush_mode(env);
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restore_snan_bit_mode(env);
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}
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static inline void fp_reset(CPUMIPSState *env)
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{
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restore_fp_status(env);
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/*
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* According to MIPS specifications, if one of the two operands is
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* a sNaN, a new qNaN has to be generated. This is done in
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* floatXX_silence_nan(). For qNaN inputs the specifications
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* says: "When possible, this QNaN result is one of the operand QNaN
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* values." In practice it seems that most implementations choose
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* the first operand if both operands are qNaN. In short this gives
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* the following rules:
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* 1. A if it is signaling
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* 2. B if it is signaling
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* 3. A (quiet)
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* 4. B (quiet)
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* A signaling NaN is always silenced before returning it.
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*/
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set_float_2nan_prop_rule(float_2nan_prop_s_ab,
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&env->active_fpu.fp_status);
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}
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/* MSA */
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enum CPUMIPSMSADataFormat {
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DF_BYTE = 0,
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DF_HALF,
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DF_WORD,
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DF_DOUBLE
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};
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static inline void restore_msa_fp_status(CPUMIPSState *env)
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{
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float_status *status = &env->active_tc.msa_fp_status;
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int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
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bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
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set_float_rounding_mode(ieee_rm[rounding_mode], status);
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set_flush_to_zero(flush_to_zero, status);
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set_flush_inputs_to_zero(flush_to_zero, status);
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}
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