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c1149f69ab
Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
129 lines
4.3 KiB
C
129 lines
4.3 KiB
C
/*
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* QEMU RISCV Hart Array
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Holds the state of a homogeneous array of RISC-V harts
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "system/reset.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/qdev-properties.h"
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#include "hw/riscv/riscv_hart.h"
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#include "qemu/error-report.h"
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static const Property riscv_harts_props[] = {
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
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DEFAULT_RSTVEC),
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/*
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* Smrnmi implementation-defined interrupt and exception trap handlers.
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*
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* When an RNMI interrupt is detected, the hart then enters M-mode and
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* jumps to the address defined by "rnmi-interrupt-vector".
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*
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* When the hart encounters an exception while executing in M-mode with
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* the mnstatus.NMIE bit clear, the hart then jumps to the address
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* defined by "rnmi-exception-vector".
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*/
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DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState,
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num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64,
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uint64_t),
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DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState,
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num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64,
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uint64_t),
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};
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static void riscv_harts_cpu_reset(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
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char *cpu_type, Error **errp)
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{
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
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qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
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if (s->harts[idx].cfg.ext_smrnmi) {
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if (idx < s->num_rnmi_irqvec) {
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qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
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"rnmi-interrupt-vector", s->rnmi_irqvec[idx]);
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}
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if (idx < s->num_rnmi_excpvec) {
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qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
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"rnmi-exception-vector", s->rnmi_excpvec[idx]);
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}
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} else {
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if (s->num_rnmi_irqvec > 0) {
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warn_report_once("rnmi-interrupt-vector property is ignored "
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"because Smrnmi extension is not enabled.");
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}
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if (s->num_rnmi_excpvec > 0) {
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warn_report_once("rnmi-exception-vector property is ignored "
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"because Smrnmi extension is not enabled.");
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}
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}
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s->harts[idx].env.mhartid = s->hartid_base + idx;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
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}
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static void riscv_harts_realize(DeviceState *dev, Error **errp)
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{
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RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
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int n;
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s->harts = g_new0(RISCVCPU, s->num_harts);
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for (n = 0; n < s->num_harts; n++) {
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if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
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return;
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}
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}
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}
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static void riscv_harts_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, riscv_harts_props);
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dc->realize = riscv_harts_realize;
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}
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static const TypeInfo riscv_harts_info = {
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.name = TYPE_RISCV_HART_ARRAY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RISCVHartArrayState),
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.class_init = riscv_harts_class_init,
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};
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static void riscv_harts_register_types(void)
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{
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type_register_static(&riscv_harts_info);
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}
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type_init(riscv_harts_register_types)
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