mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 18:44:58 -06:00
6b56bb6dbc
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its xscom register set. This adds support for PHB4/5. skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(), which shows up as unimplemented xscom reads. Set a value in PCI CONF1 register's link-width field to demonstrate skiboot doing something interesting with it. In the bigger picture, it might be better to model the pervasive chiplet type as parent that each non-core chiplet model derives from. For now this is enough to get the PHB registers implemented and working for skiboot, and provides a second example (after the N1 chiplet) that will help if the design is reworked as such. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> |
||
|---|---|---|
| .. | ||
| articia.h | ||
| astro.h | ||
| bonito.h | ||
| designware.h | ||
| dino.h | ||
| fsl_imx8m_phy.h | ||
| gpex.h | ||
| grackle.h | ||
| i440fx.h | ||
| ls7a.h | ||
| mv64361.h | ||
| pam.h | ||
| pnv_phb3.h | ||
| pnv_phb3_regs.h | ||
| pnv_phb4.h | ||
| pnv_phb4_regs.h | ||
| ppc4xx.h | ||
| ppce500.h | ||
| q35.h | ||
| remote.h | ||
| sabre.h | ||
| spapr.h | ||
| uninorth.h | ||
| xilinx-pcie.h | ||