Wilfred Mallawa bf8803c64d hw/riscv: opentitan: bump opentitan version ... The following patch updates opentitan to match the new configuration, as per, lowRISC/opentitan@217a0168ba Note: with this patch we now skip the usage of the opentitan `boot_rom`. The Opentitan boot rom contains hw verification for devies which we are currently not supporting in qemu. As of now, the `boot_rom` has no major significance, however, would be good to support in the future. Tested by running utests from the latest tock [1] (that supports this version of OT). [1] https://github.com/tock/tock/pull/3056 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-09-07 09:18:33 +02:00
..
boot.h	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
boot_opensbi.h	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	hw/riscv: opentitan: bump opentitan version	2022-09-07 09:18:33 +02:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
shakti_c.h	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00
spike.h	hw/riscv: spike: Allow using binary firmware as bios	2022-01-21 15:52:56 +10:00
virt.h	hw/riscv: virt: Create a platform bus	2022-04-29 10:48:31 +10:00