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5f64adc138
* handle FTYPE flag correctly in v7M exception return
for v7M CPUs with an FPU (v8M CPUs were already correct)
* versal: Add the CRP as unimplemented
* Fix ISR_EL1 tracking when executing at EL2
* Honor HCR_EL2.TID3 trapping requirements
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191126' into staging
target-arm queue:
* handle FTYPE flag correctly in v7M exception return
for v7M CPUs with an FPU (v8M CPUs were already correct)
* versal: Add the CRP as unimplemented
* Fix ISR_EL1 tracking when executing at EL2
* Honor HCR_EL2.TID3 trapping requirements
# gpg: Signature made Tue 26 Nov 2019 14:11:50 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20191126:
target/arm: Honor HCR_EL2.TID3 trapping requirements
target/arm: Fix ISR_EL1 tracking when executing at EL2
hw/arm: versal: Add the CRP as unimplemented
target/arm: Fix handling of cortex-m FTYPE flag in EXCRET
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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