Richard Henderson ca5bed07d0 tcg/ppc: Use new registers for LQ destination ... LQ has a constraint that RTp != RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-stable@nongnu.org Fixes: 526cd4ec01 ("tcg/ppc: Support 128-bit load/store") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-01-11 08:47:45 +11:00
..
tcg-target-con-set.h	tcg/ppc: Use new registers for LQ destination	2024-01-11 08:47:45 +11:00
tcg-target-con-str.h	tcg/ppc: Support 128-bit load/store	2023-05-30 09:51:11 -07:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/ppc: Use new registers for LQ destination	2024-01-11 08:47:45 +11:00
tcg-target.h	tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}	2023-11-06 08:27:21 -08:00
tcg-target.opc.h	tcg/ppc: Implement INDEX_op_rot[lr]v_vec	2020-06-02 08:42:37 -07:00