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8201f1a29c
By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
47 lines
1 KiB
C
47 lines
1 KiB
C
/*
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* ARM cpu parameters for qemu.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.0-or-later
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*/
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#ifndef ARM_CPU_PARAM_H
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#define ARM_CPU_PARAM_H
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#ifdef TARGET_AARCH64
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# define TARGET_PHYS_ADDR_SPACE_BITS 52
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# define TARGET_VIRT_ADDR_SPACE_BITS 52
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#else
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#ifdef CONFIG_USER_ONLY
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# ifdef TARGET_AARCH64
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# define TARGET_TAGGED_ADDRESSES
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# ifdef __FreeBSD__
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# define TARGET_PAGE_BITS 12
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# else
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/* Allow user-only to vary page size from 4k */
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# define TARGET_PAGE_BITS_VARY
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# endif
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# else
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# define TARGET_PAGE_BITS 12
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# endif
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#else /* !CONFIG_USER_ONLY */
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/*
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* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
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* have to support 1K tiny pages.
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*/
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# define TARGET_PAGE_BITS_VARY
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# define TARGET_PAGE_BITS_LEGACY 10
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#endif /* !CONFIG_USER_ONLY */
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/*
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* ARM-specific extra insn start words:
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* 1: Conditional execution bits
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* 2: Partial exception syndrome for data aborts
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*/
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#define TARGET_INSN_START_EXTRA_WORDS 2
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#endif
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