mirror of
https://github.com/Motorhead1991/qemu.git
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b29b11b51f
Adds restrict qualifier to HVX pointer arguments. This will allow the compiler to produce better optimized code, as input vectors are now assumed not to alias, and no runtime aliasing checks will be required. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
356 lines
14 KiB
C
356 lines
14 KiB
C
/*
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_MMVEC_MACROS_H
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#define HEXAGON_MMVEC_MACROS_H
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#include "qemu/host-utils.h"
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#include "arch.h"
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#include "mmvec/system_ext_mmvec.h"
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#ifndef QEMU_GENERATE
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#define VdV (*(MMVector *restrict)(VdV_void))
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#define VsV (*(MMVector *restrict)(VsV_void))
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#define VuV (*(MMVector *restrict)(VuV_void))
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#define VvV (*(MMVector *restrict)(VvV_void))
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#define VwV (*(MMVector *restrict)(VwV_void))
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#define VxV (*(MMVector *restrict)(VxV_void))
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#define VyV (*(MMVector *restrict)(VyV_void))
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#define VddV (*(MMVectorPair *restrict)(VddV_void))
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#define VuuV (*(MMVectorPair *restrict)(VuuV_void))
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#define VvvV (*(MMVectorPair *restrict)(VvvV_void))
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#define VxxV (*(MMVectorPair *restrict)(VxxV_void))
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#define QeV (*(MMQReg *restrict)(QeV_void))
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#define QdV (*(MMQReg *restrict)(QdV_void))
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#define QsV (*(MMQReg *restrict)(QsV_void))
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#define QtV (*(MMQReg *restrict)(QtV_void))
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#define QuV (*(MMQReg *restrict)(QuV_void))
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#define QvV (*(MMQReg *restrict)(QvV_void))
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#define QxV (*(MMQReg *restrict)(QxV_void))
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#endif
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#define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \
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do { \
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env->vtcm_log.data.ub[IDX] = (VAL); \
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if (MASK) { \
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set_bit((IDX), env->vtcm_log.mask); \
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} else { \
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clear_bit((IDX), env->vtcm_log.mask); \
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} \
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env->vtcm_log.va[IDX] = (VA); \
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} while (0)
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#define fNOTQ(VAL) \
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({ \
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MMQReg _ret; \
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int _i_; \
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for (_i_ = 0; _i_ < fVECSIZE() / 64; _i_++) { \
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_ret.ud[_i_] = ~VAL.ud[_i_]; \
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} \
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_ret;\
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})
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#define fGETQBITS(REG, WIDTH, MASK, BITNO) \
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((MASK) & (REG.w[(BITNO) >> 5] >> ((BITNO) & 0x1f)))
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#define fGETQBIT(REG, BITNO) fGETQBITS(REG, 1, 1, BITNO)
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#define fGENMASKW(QREG, IDX) \
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(((fGETQBIT(QREG, (IDX * 4 + 0)) ? 0xFF : 0x0) << 0) | \
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((fGETQBIT(QREG, (IDX * 4 + 1)) ? 0xFF : 0x0) << 8) | \
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((fGETQBIT(QREG, (IDX * 4 + 2)) ? 0xFF : 0x0) << 16) | \
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((fGETQBIT(QREG, (IDX * 4 + 3)) ? 0xFF : 0x0) << 24))
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#define fGETNIBBLE(IDX, SRC) (fSXTN(4, 8, (SRC >> (4 * IDX)) & 0xF))
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#define fGETCRUMB(IDX, SRC) (fSXTN(2, 8, (SRC >> (2 * IDX)) & 0x3))
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#define fGETCRUMB_SYMMETRIC(IDX, SRC) \
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((fGETCRUMB(IDX, SRC) >= 0 ? (2 - fGETCRUMB(IDX, SRC)) \
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: fGETCRUMB(IDX, SRC)))
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#define fGENMASKH(QREG, IDX) \
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(((fGETQBIT(QREG, (IDX * 2 + 0)) ? 0xFF : 0x0) << 0) | \
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((fGETQBIT(QREG, (IDX * 2 + 1)) ? 0xFF : 0x0) << 8))
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#define fGETMASKW(VREG, QREG, IDX) (VREG.w[IDX] & fGENMASKW((QREG), IDX))
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#define fGETMASKH(VREG, QREG, IDX) (VREG.h[IDX] & fGENMASKH((QREG), IDX))
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#define fCONDMASK8(QREG, IDX, YESVAL, NOVAL) \
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(fGETQBIT(QREG, IDX) ? (YESVAL) : (NOVAL))
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#define fCONDMASK16(QREG, IDX, YESVAL, NOVAL) \
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((fGENMASKH(QREG, IDX) & (YESVAL)) | \
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(fGENMASKH(fNOTQ(QREG), IDX) & (NOVAL)))
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#define fCONDMASK32(QREG, IDX, YESVAL, NOVAL) \
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((fGENMASKW(QREG, IDX) & (YESVAL)) | \
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(fGENMASKW(fNOTQ(QREG), IDX) & (NOVAL)))
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#define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \
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do { \
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uint32_t __TMP = (VAL); \
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REG.w[(BITNO) >> 5] &= ~((MASK) << ((BITNO) & 0x1f)); \
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REG.w[(BITNO) >> 5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); \
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} while (0)
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#define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL)
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#define fVBYTES() (fVECSIZE())
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#define fVALIGN(ADDR, LOG2_ALIGNMENT) (ADDR = ADDR & ~(LOG2_ALIGNMENT - 1))
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#define fVLASTBYTE(ADDR, LOG2_ALIGNMENT) (ADDR = ADDR | (LOG2_ALIGNMENT - 1))
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#define fVELEM(WIDTH) ((fVECSIZE() * 8) / WIDTH)
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#define fVECLOGSIZE() (7)
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#define fVECSIZE() (1 << fVECLOGSIZE())
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#define fSWAPB(A, B) do { uint8_t tmp = A; A = B; B = tmp; } while (0)
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#define fV_AL_CHECK(EA, MASK) \
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if ((EA) & (MASK)) { \
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warn("aligning misaligned vector. EA=%08x", (EA)); \
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}
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#define fSCATTER_INIT(REGION_START, LENGTH, ELEMENT_SIZE) \
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mem_vector_scatter_init(env)
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#define fGATHER_INIT(REGION_START, LENGTH, ELEMENT_SIZE) \
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mem_vector_gather_init(env)
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#define fSCATTER_FINISH(OP)
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#define fGATHER_FINISH()
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#define fLOG_SCATTER_OP(SIZE) \
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do { \
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env->vtcm_log.op = true; \
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env->vtcm_log.op_size = SIZE; \
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} while (0)
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#define fVLOG_VTCM_WORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 4; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC. ub[4 * IDX + i0], \
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4 * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_HALFWORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 2; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \
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2 * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_HALFWORD_INCREMENT_DV(EA, OFFSET, INC, IDX, IDX2, IDX_H, \
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ALIGNMENT, LEN) \
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do { \
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int log_byte = 0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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for (int i0 = 0; i0 < 2; i0++) { \
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log_byte = (va + i0) <= va_high; \
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LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \
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2 * IDX + i0); \
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} \
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} while (0)
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/* NOTE - Will this always be tmp_VRegs[0]; */
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#define GATHER_FUNCTION(EA, OFFSET, IDX, LEN, ELEMENT_SIZE, BANK_IDX, QVAL) \
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do { \
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int i0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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uintptr_t ra = GETPC(); \
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int log_byte = 0; \
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for (i0 = 0; i0 < ELEMENT_SIZE; i0++) { \
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log_byte = ((va + i0) <= va_high) && QVAL; \
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uint8_t B; \
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B = cpu_ldub_data_ra(env, EA + i0, ra); \
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env->tmp_VRegs[0].ub[ELEMENT_SIZE * IDX + i0] = B; \
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LOG_VTCM_BYTE(va + i0, log_byte, B, ELEMENT_SIZE * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_GATHER_WORD(EA, OFFSET, IDX, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORD(EA, OFFSET, IDX, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORD_DV(EA, OFFSET, IDX, IDX2, IDX_H, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), 1); \
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} while (0)
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#define fVLOG_VTCM_GATHER_WORDQ(EA, OFFSET, IDX, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \
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fGETQBIT(QsV, 4 * IDX + i0)); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORDQ(EA, OFFSET, IDX, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \
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fGETQBIT(QsV, 2 * IDX + i0)); \
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} while (0)
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#define fVLOG_VTCM_GATHER_HALFWORDQ_DV(EA, OFFSET, IDX, IDX2, IDX_H, Q, LEN) \
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do { \
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GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \
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fGETQBIT(QsV, 2 * IDX + i0)); \
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} while (0)
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#define SCATTER_OP_WRITE_TO_MEM(TYPE) \
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do { \
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ra = GETPC(); \
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for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
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if (test_bit(i, env->vtcm_log.mask)) { \
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TYPE dst = 0; \
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TYPE inc = 0; \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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uint8_t val; \
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val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra); \
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dst |= val << (8 * j); \
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inc |= env->vtcm_log.data.ub[j + i] << (8 * j); \
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clear_bit(j + i, env->vtcm_log.mask); \
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env->vtcm_log.data.ub[j + i] = 0; \
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} \
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dst += inc; \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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cpu_stb_data_ra(env, env->vtcm_log.va[i + j], \
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(dst >> (8 * j)) & 0xFF, ra); \
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} \
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} \
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} \
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} while (0)
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#define SCATTER_OP_PROBE_MEM(TYPE, MMU_IDX, RETADDR) \
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do { \
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for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \
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if (test_bit(i, env->vtcm_log.mask)) { \
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for (int j = 0; j < sizeof(TYPE); j++) { \
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probe_read(env, env->vtcm_log.va[i + j], 1, \
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MMU_IDX, RETADDR); \
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probe_write(env, env->vtcm_log.va[i + j], 1, \
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MMU_IDX, RETADDR); \
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} \
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} \
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} \
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} while (0)
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#define SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, ELEM_SIZE, BANK_IDX, QVAL, IN) \
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do { \
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int i0; \
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target_ulong va = EA; \
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target_ulong va_high = EA + LEN; \
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int log_byte = 0; \
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for (i0 = 0; i0 < ELEM_SIZE; i0++) { \
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log_byte = ((va + i0) <= va_high) && QVAL; \
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LOG_VTCM_BYTE(va + i0, log_byte, IN.ub[ELEM_SIZE * IDX + i0], \
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ELEM_SIZE * IDX + i0); \
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} \
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} while (0)
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#define fVLOG_VTCM_HALFWORD(EA, OFFSET, IN, IDX, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1, IN); \
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} while (0)
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#define fVLOG_VTCM_WORD(EA, OFFSET, IN, IDX, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1, IN); \
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} while (0)
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#define fVLOG_VTCM_HALFWORDQ(EA, OFFSET, IN, IDX, Q, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \
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fGETQBIT(QsV, 2 * IDX + i0), IN); \
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} while (0)
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#define fVLOG_VTCM_WORDQ(EA, OFFSET, IN, IDX, Q, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \
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fGETQBIT(QsV, 4 * IDX + i0), IN); \
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} while (0)
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#define fVLOG_VTCM_HALFWORD_DV(EA, OFFSET, IN, IDX, IDX2, IDX_H, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, \
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(2 * IDX2 + IDX_H), 1, IN); \
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} while (0)
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#define fVLOG_VTCM_HALFWORDQ_DV(EA, OFFSET, IN, IDX, Q, IDX2, IDX_H, LEN) \
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do { \
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SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \
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fGETQBIT(QsV, 2 * IDX + i0), IN); \
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} while (0)
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#define fSTORERELEASE(EA, TYPE) \
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do { \
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fV_AL_CHECK(EA, fVECSIZE() - 1); \
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} while (0)
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#ifdef QEMU_GENERATE
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#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true)
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#endif
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#ifdef QEMU_GENERATE
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#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false)
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#endif
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#ifdef QEMU_GENERATE
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#define fSTOREMMV(EA, SRC) \
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gen_vreg_store(ctx, EA, SRC##_off, insn->slot, true)
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#endif
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#ifdef QEMU_GENERATE
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#define fSTOREMMVQ(EA, SRC, MASK) \
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gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, false)
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#endif
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#ifdef QEMU_GENERATE
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#define fSTOREMMVNQ(EA, SRC, MASK) \
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gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, true)
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#endif
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#ifdef QEMU_GENERATE
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#define fSTOREMMVU(EA, SRC) \
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gen_vreg_store(ctx, EA, SRC##_off, insn->slot, false)
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#endif
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#define fVFOREACH(WIDTH, VAR) for (VAR = 0; VAR < fVELEM(WIDTH); VAR++)
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#define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \
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ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX) % \
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(fVECSIZE() / (sizeof(ARRAY.TYPE[0])))]
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#define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V)))
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#define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31))
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#define fVUADDSAT(WIDTH, U, V) \
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fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V))
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#define fVSADDSAT(WIDTH, U, V) \
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fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V))
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#define fVUSUBSAT(WIDTH, U, V) \
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fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V))
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#define fVSSUBSAT(WIDTH, U, V) \
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fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V))
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#define fVAVGU(WIDTH, U, V) \
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((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
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#define fVAVGURND(WIDTH, U, V) \
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((fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
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#define fVNAVGU(WIDTH, U, V) \
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((fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V)) >> 1)
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#define fVNAVGURNDSAT(WIDTH, U, V) \
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fVSATUN(WIDTH, ((fZXTN(WIDTH, 2 * WIDTH, U) - \
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fZXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1))
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#define fVAVGS(WIDTH, U, V) \
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((fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V)) >> 1)
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#define fVAVGSRND(WIDTH, U, V) \
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((fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
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#define fVNAVGS(WIDTH, U, V) \
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((fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V)) >> 1)
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#define fVNAVGSRND(WIDTH, U, V) \
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((fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1)
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#define fVNAVGSRNDSAT(WIDTH, U, V) \
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fVSATN(WIDTH, ((fSXTN(WIDTH, 2 * WIDTH, U) - \
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fSXTN(WIDTH, 2 * WIDTH, V) + 1) >> 1))
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#define fVNOROUND(VAL, SHAMT) VAL
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#define fVNOSAT(VAL) VAL
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#define fVROUND(VAL, SHAMT) \
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((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
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#define fCARRY_FROM_ADD32(A, B, C) \
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(((fZXTN(32, 64, A) + fZXTN(32, 64, B) + C) >> 32) & 1)
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#define fUARCH_NOTE_PUMP_4X()
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#define fUARCH_NOTE_PUMP_2X()
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#define IV1DEAD()
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#define fGET10BIT(COE, VAL, POS) \
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do { \
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COE = (sextract32(VAL, 24 + 2 * POS, 2) << 8) | \
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extract32(VAL, POS * 8, 8); \
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} while (0);
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#endif
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