qemu/target/riscv
Daniel Henrique Barboza 289dcab554 target/riscv/kvm: add kvm_csr_cfgs[]
At this moment we're not checking if the host has support for any
specific CSR before doing get/put regs. This will cause problems if the
host KVM doesn't support it (see [1] as an example).

We'll use the same approach done with the CPU extensions: read all known
KVM CSRs during init() to check for availability, then read/write them
if they are present. This will be made by either using get-reglist or by
directly reading the CSRs.

For now we'll just convert the CSRs to use a kvm_csr_cfg[] array,
reusing the same KVMCPUConfig abstraction we use for extensions, and use
the array in (get|put)_csr_regs() instead of manually listing them. A
lot of boilerplate will be added but at least we'll automate the get/put
procedure for CSRs, i.e. adding a new CSR in the future will be a matter
of adding it in kvm_csr_regs[] and everything else will be taken care
of.

Despite all the code changes no behavioral change is made.

[1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBLbLKhfv=+jb0SYAw@mail.gmail.com/

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250429124421.223883-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
(cherry picked from commit d3b6f1742c)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-05-25 13:14:52 +03:00
..
insn_trans target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions 2025-05-20 09:59:09 +03:00
kvm target/riscv/kvm: add kvm_csr_cfgs[] 2025-05-25 13:14:52 +03:00
tcg target/riscv: AMO operations always raise store/AMO fault 2024-10-30 11:22:08 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu-param.h license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later 2024-09-20 10:11:59 +03:00
cpu-qom.h target/riscv: Add max32 CPU for RV64 QEMU 2024-10-30 11:22:07 +10:00
cpu.c target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set 2025-03-18 09:02:47 +03:00
cpu.h target/riscv/kvm: add kvm_csr_cfgs[] 2025-05-25 13:14:52 +03:00
cpu_bits.h target/riscv: implement zicfiss instructions 2024-10-30 11:22:08 +10:00
cpu_cfg.h target/riscv: Add zicfiss extension 2024-10-30 11:22:08 +10:00
cpu_helper.c target/riscv: fix endless translation loop on big endian systems 2025-05-20 09:55:46 +03:00
cpu_user.h target/riscv: zicfilp lpad impl and branch tracking 2024-10-30 11:22:08 +10:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: fix access permission checks for CSR_SSP 2025-03-24 07:46:14 +03:00
debug.c target/riscv/debug.c: use wp size = 4 for 32-bit CPUs 2025-03-18 09:02:47 +03:00
debug.h target/riscv: Add textra matching condition for the triggers 2024-10-02 15:11:51 +10:00
fpu_helper.c target/riscv: Fix froundnx.h nanbox check 2024-06-26 23:02:35 +10:00
gdbstub.c riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() 2024-06-03 11:12:12 +10:00
helper.h target/riscv: Raise exceptions on wrs.nto 2024-06-03 11:12:11 +10:00
insn16.decode target/riscv: compressed encodings for sspush and sspopchk 2024-10-30 11:22:08 +10:00
insn32.decode target/riscv: Fix the rvv reserved encoding of unmasked instructions 2025-05-20 09:59:14 +03:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: mmu changes for zicfiss shadow stack protection 2024-10-30 11:22:08 +10:00
Kconfig target/riscv/cpu_helper: Fix linking problem with semihosting disabled 2024-10-02 15:11:51 +10:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: introduce ssp and enabling controls for zicfiss 2024-10-30 11:22:08 +10:00
meson.build riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
monitor.c target/riscv: remove break after g_assert_not_reached() 2024-09-24 13:53:35 +02:00
op_helper.c target/riscv: save and restore elp state on priv transitions 2024-10-30 11:22:08 +10:00
pmp.c target/riscv: pmp: move Smepmp operation conversion into a function 2025-05-20 09:54:28 +03:00
pmp.h target/riscv: Introduce elp state and enabling controls for zicfilp 2024-10-30 11:22:08 +10:00
pmu.c target/riscv: Add asserts for out-of-bound access 2024-08-06 14:20:16 +10:00
pmu.h target/riscv: More accurately model priv mode filtering. 2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c target: Improve error reporting for CpuModelInfo member @props 2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h target/riscv/kvm: implement SBI debug console (DBCN) calls 2024-06-03 11:12:11 +10:00
th_csr.c riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
time_helper.c target/riscv: Stop timer with infinite timecmp 2024-10-02 15:11:51 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: implement zicfiss instructions 2024-10-30 11:22:08 +10:00
vcrypto_helper.c target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter 2025-03-24 14:21:24 +03:00
vector_helper.c target/riscv: Fix vslidedown with rvv_ta_all_1s 2025-05-20 09:59:28 +03:00
vector_internals.c target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter 2025-03-24 14:21:24 +03:00
vector_internals.h target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter 2025-03-24 14:21:24 +03:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00