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The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-5-peter.maydell@linaro.org |
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| .. | ||
| allwinner-a10-pic.c | ||
| apic.c | ||
| apic_common.c | ||
| arm_gic.c | ||
| arm_gic_common.c | ||
| arm_gic_kvm.c | ||
| arm_gicv2m.c | ||
| arm_gicv3.c | ||
| arm_gicv3_common.c | ||
| arm_gicv3_cpuif.c | ||
| arm_gicv3_dist.c | ||
| arm_gicv3_its_common.c | ||
| arm_gicv3_its_kvm.c | ||
| arm_gicv3_kvm.c | ||
| arm_gicv3_redist.c | ||
| armv7m_nvic.c | ||
| aspeed_vic.c | ||
| bcm2835_ic.c | ||
| bcm2836_control.c | ||
| etraxfs_pic.c | ||
| exynos4210_combiner.c | ||
| exynos4210_gic.c | ||
| gic_internal.h | ||
| gicv3_internal.h | ||
| grlib_irqmp.c | ||
| heathrow_pic.c | ||
| i8259.c | ||
| i8259_common.c | ||
| imx_avic.c | ||
| imx_gpcv2.c | ||
| intc.c | ||
| ioapic.c | ||
| ioapic_common.c | ||
| lm32_pic.c | ||
| Makefile.objs | ||
| mips_gic.c | ||
| nios2_iic.c | ||
| omap_intc.c | ||
| ompic.c | ||
| openpic.c | ||
| openpic_kvm.c | ||
| pl190.c | ||
| puv3_intc.c | ||
| realview_gic.c | ||
| s390_flic.c | ||
| s390_flic_kvm.c | ||
| sh_intc.c | ||
| slavio_intctl.c | ||
| trace-events | ||
| vgic_common.h | ||
| xics.c | ||
| xics_kvm.c | ||
| xics_pnv.c | ||
| xics_spapr.c | ||
| xilinx_intc.c | ||
| xlnx-pmu-iomod-intc.c | ||
| xlnx-zynqmp-ipi.c | ||