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ad80e36744
We pass a ResetType argument to the Resettable class enter
phase method, but we don't pass it to hold and exit, even though
the callsites have it readily available. This means that if
a device cared about the ResetType it would need to record it
in the enter phase method to use later on. Pass the type to
all three of the phase methods to avoid having to do that.
Commit created with
for dir in hw target include; do \
spatch --macro-file scripts/cocci-macro-file.h \
--sp-file scripts/coccinelle/reset-type.cocci \
--keep-comments --smpl-spacing --in-place \
--include-headers --dir $dir; done
and no manual edits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
290 lines
8.2 KiB
C
290 lines
8.2 KiB
C
/*
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* STM32L4x5 EXTI (Extended interrupts and events controller)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Samuel Tardieu <samuel.tardieu@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This work is based on the stm32f4xx_exti by Alistair Francis.
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* Original code is licensed under the MIT License:
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*/
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/*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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* https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32l4x5_exti.h"
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#define EXTI_IMR1 0x00
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#define EXTI_EMR1 0x04
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#define EXTI_RTSR1 0x08
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#define EXTI_FTSR1 0x0C
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#define EXTI_SWIER1 0x10
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#define EXTI_PR1 0x14
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#define EXTI_IMR2 0x20
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#define EXTI_EMR2 0x24
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#define EXTI_RTSR2 0x28
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#define EXTI_FTSR2 0x2C
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#define EXTI_SWIER2 0x30
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#define EXTI_PR2 0x34
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#define EXTI_NUM_GPIO_EVENT_IN_LINES 16
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#define EXTI_MAX_IRQ_PER_BANK 32
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#define EXTI_IRQS_BANK0 32
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#define EXTI_IRQS_BANK1 8
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static const unsigned irqs_per_bank[EXTI_NUM_REGISTER] = {
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EXTI_IRQS_BANK0,
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EXTI_IRQS_BANK1,
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};
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static const uint32_t exti_romask[EXTI_NUM_REGISTER] = {
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0xff820000, /* 0b11111111_10000010_00000000_00000000 */
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0x00000087, /* 0b00000000_00000000_00000000_10000111 */
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};
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static unsigned regbank_index_by_irq(unsigned irq)
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{
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return irq >= EXTI_MAX_IRQ_PER_BANK ? 1 : 0;
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}
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static unsigned regbank_index_by_addr(hwaddr addr)
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{
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return addr >= EXTI_IMR2 ? 1 : 0;
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}
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static unsigned valid_mask(unsigned bank)
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{
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return MAKE_64BIT_MASK(0, irqs_per_bank[bank]);
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}
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static unsigned configurable_mask(unsigned bank)
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{
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return valid_mask(bank) & ~exti_romask[bank];
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}
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static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type)
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{
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Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj);
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for (unsigned bank = 0; bank < EXTI_NUM_REGISTER; bank++) {
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s->imr[bank] = exti_romask[bank];
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s->emr[bank] = 0x00000000;
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s->rtsr[bank] = 0x00000000;
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s->ftsr[bank] = 0x00000000;
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s->swier[bank] = 0x00000000;
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s->pr[bank] = 0x00000000;
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}
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}
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static void stm32l4x5_exti_set_irq(void *opaque, int irq, int level)
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{
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Stm32l4x5ExtiState *s = opaque;
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const unsigned bank = regbank_index_by_irq(irq);
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const int oirq = irq;
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trace_stm32l4x5_exti_set_irq(irq, level);
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/* Shift the value to enable access in x2 registers. */
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irq %= EXTI_MAX_IRQ_PER_BANK;
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/* If the interrupt is masked, pr won't be raised */
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if (!extract32(s->imr[bank], irq, 1)) {
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return;
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}
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if (((1 << irq) & s->rtsr[bank]) && level) {
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/* Rising Edge */
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s->pr[bank] |= 1 << irq;
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qemu_irq_pulse(s->irq[oirq]);
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} else if (((1 << irq) & s->ftsr[bank]) && !level) {
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/* Falling Edge */
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s->pr[bank] |= 1 << irq;
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qemu_irq_pulse(s->irq[oirq]);
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}
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/*
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* In the following situations :
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* - falling edge but rising trigger selected
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* - rising edge but falling trigger selected
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* - no trigger selected
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* No action is required
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*/
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}
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static uint64_t stm32l4x5_exti_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Stm32l4x5ExtiState *s = opaque;
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uint32_t r = 0;
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const unsigned bank = regbank_index_by_addr(addr);
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switch (addr) {
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case EXTI_IMR1:
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case EXTI_IMR2:
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r = s->imr[bank];
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break;
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case EXTI_EMR1:
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case EXTI_EMR2:
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r = s->emr[bank];
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break;
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case EXTI_RTSR1:
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case EXTI_RTSR2:
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r = s->rtsr[bank];
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break;
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case EXTI_FTSR1:
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case EXTI_FTSR2:
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r = s->ftsr[bank];
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break;
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case EXTI_SWIER1:
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case EXTI_SWIER2:
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r = s->swier[bank];
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break;
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case EXTI_PR1:
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case EXTI_PR2:
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r = s->pr[bank];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"STM32L4X5_exti_read: Bad offset 0x%" HWADDR_PRIx "\n",
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addr);
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break;
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}
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trace_stm32l4x5_exti_read(addr, r);
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return r;
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}
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static void stm32l4x5_exti_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Stm32l4x5ExtiState *s = opaque;
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const unsigned bank = regbank_index_by_addr(addr);
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trace_stm32l4x5_exti_write(addr, val64);
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switch (addr) {
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case EXTI_IMR1:
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case EXTI_IMR2:
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s->imr[bank] = val64 & valid_mask(bank);
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return;
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case EXTI_EMR1:
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case EXTI_EMR2:
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s->emr[bank] = val64 & valid_mask(bank);
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return;
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case EXTI_RTSR1:
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case EXTI_RTSR2:
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s->rtsr[bank] = val64 & configurable_mask(bank);
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return;
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case EXTI_FTSR1:
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case EXTI_FTSR2:
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s->ftsr[bank] = val64 & configurable_mask(bank);
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return;
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case EXTI_SWIER1:
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case EXTI_SWIER2: {
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const uint32_t set = val64 & configurable_mask(bank);
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const uint32_t pend = set & ~s->swier[bank] & s->imr[bank] &
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~s->pr[bank];
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s->swier[bank] = set;
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s->pr[bank] |= pend;
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for (unsigned i = 0; i < irqs_per_bank[bank]; i++) {
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if (extract32(pend, i, 1)) {
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qemu_irq_pulse(s->irq[i + 32 * bank]);
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}
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}
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return;
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}
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case EXTI_PR1:
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case EXTI_PR2: {
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const uint32_t cleared = s->pr[bank] & val64 & configurable_mask(bank);
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/* This bit is cleared by writing a 1 to it */
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s->pr[bank] &= ~cleared;
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/* Software triggered interrupts are cleared as well */
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s->swier[bank] &= ~cleared;
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return;
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"STM32L4X5_exti_write: Bad offset 0x%" HWADDR_PRIx "\n",
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addr);
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}
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}
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static const MemoryRegionOps stm32l4x5_exti_ops = {
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.read = stm32l4x5_exti_read,
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.write = stm32l4x5_exti_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.impl.unaligned = false,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void stm32l4x5_exti_init(Object *obj)
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{
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Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj);
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for (size_t i = 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
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}
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memory_region_init_io(&s->mmio, obj, &stm32l4x5_exti_ops, s,
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TYPE_STM32L4X5_EXTI, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq,
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EXTI_NUM_GPIO_EVENT_IN_LINES);
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}
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static const VMStateDescription vmstate_stm32l4x5_exti = {
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.name = TYPE_STM32L4X5_EXTI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(imr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_UINT32_ARRAY(emr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_UINT32_ARRAY(rtsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_UINT32_ARRAY(ftsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_UINT32_ARRAY(swier, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_UINT32_ARRAY(pr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stm32l4x5_exti_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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dc->vmsd = &vmstate_stm32l4x5_exti;
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rc->phases.hold = stm32l4x5_exti_reset_hold;
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}
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static const TypeInfo stm32l4x5_exti_types[] = {
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{
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.name = TYPE_STM32L4X5_EXTI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Stm32l4x5ExtiState),
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.instance_init = stm32l4x5_exti_init,
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.class_init = stm32l4x5_exti_class_init,
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}
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};
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DEFINE_TYPES(stm32l4x5_exti_types)
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