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f50d0f335a
Expose riscv_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250405161320.76854-2-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* riscv TCG cpu class initialization
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*
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* Copyright (c) 2023 Ventana Micro Systems Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_TCG_CPU_H
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#define RISCV_TCG_CPU_H
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#include "cpu.h"
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void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
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void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
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bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
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extern const TCGCPUOps riscv_tcg_ops;
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struct DisasContext;
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struct RISCVCPUConfig;
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typedef struct RISCVDecoder {
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bool (*guard_func)(const struct RISCVCPUConfig *);
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bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
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} RISCVDecoder;
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typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
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extern const size_t decoder_table_size;
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extern const RISCVDecoder decoder_table[];
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void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
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#endif
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