qemu/target/arm
Akihiko Odaki bedcc7465d target/arm: Define raw write for PMU CLR registers
Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their
default write function, which clears written bits instead of writes the
raw value.

PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead
had ARM_CP_NO_RAW. Commit 7a0e58fa64 ("target-arm: Split NO_MIGRATE
into ALIAS and NO_RAW") sugguests ARM_CP_ALIAS should be used instead of
ARM_CP_NO_RAW in such a case:

> We currently mark ARM coprocessor/system register definitions with
> the flag ARM_CP_NO_MIGRATE for two different reasons:
> 1) register is an alias on to state that's also visible via
>    some other register, and that other register is the one
>    responsible for migrating the state
> 2) register is not actually state at all (for instance the TLB
>    or cache maintenance operation "registers") and it makes no
>    sense to attempt to migrate it or otherwise access the raw state
>
> This works fine for identifying which registers should be ignored
> when performing migration, but we also use the same functions for
> synchronizing system register state between QEMU and the kernel
> when using KVM. In this case we don't want to try to sync state
> into registers in category 2, but we do want to sync into registers
> in category 1, because the kernel might have picked a different
> one of the aliases as its choice for which one to expose for
> migration.

These registers fall in category 1 (ARM_CP_ALIAS), not category 2
(ARM_CP_NO_RAW).

ARM_CP_NO_RAW also has another undesired side effect that hides
registers from GDB.

Properly set raw write functions and drop the ARM_CP_NO_RAW flag from
PMINTENCLR and PMINTENCLR_EL1; this fixes GDB/KVM state synchronization
of PMCNTENCLR and PMCNTENCLR_EL0, and exposes all these four registers
to GDB.

It is not necessary to add ARM_CP_ALIAS to these registers because the
flag is already set.

Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Message-id: 20250531-clr-v3-1-377f9bf1746d@rsg.ci.i.u-tokyo.ac.jp
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-13 11:03:20 +01:00
..
hvf hvf: avoid repeatedly setting trap debug for each cpu 2025-05-06 15:01:22 +01:00
tcg target/arm: Only link with zlib when TCG is enabled 2025-05-29 17:45:11 +01:00
arch_dump.c target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-14 15:12:40 +01:00
arm-powerctl.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
arm-qmp-cmds.c target/arm/qmp: Include missing 'cpu.h' header 2025-05-29 17:45:12 +01:00
common-semi-target.h target/arm/common-semi-target.h: Remove unnecessary boot.h include 2023-10-19 14:32:13 +01:00
cortex-regs.c target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing 2023-05-18 11:39:33 +01:00
cpregs.h target/arm/cpregs: Include missing 'target/arm/cpu.h' header 2025-05-29 17:45:11 +01:00
cpu-features.h target/arm/cpu-features: Include missing 'cpu.h' header 2025-05-29 17:45:11 +01:00
cpu-param.h accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr 2025-05-05 09:24:10 -07:00
cpu-qom.h target/arm: Remove TYPE_AARCH64_CPU 2025-05-14 14:29:46 +01:00
cpu.c target/arm: Fill in TCGCPUOps.pointer_wrap 2025-05-28 08:08:48 +01:00
cpu.h target/arm: Remove TYPE_AARCH64_CPU 2025-05-14 14:29:46 +01:00
cpu32-stubs.c target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features 2025-05-14 15:12:40 +01:00
cpu64.c target/arm: Remove TYPE_AARCH64_CPU 2025-05-14 14:29:46 +01:00
debug_helper.c target/arm/debug_helper: remove target_ulong 2025-05-14 15:12:40 +01:00
gdbstub.c target/arm: Handle AArch64 gdb read/write regs in TYPE_ARM_CPU 2025-04-25 17:00:42 +02:00
gdbstub64.c exec/cpu-all: remove exec/target_page include 2025-04-23 15:04:57 -07:00
gtimer.h target/arm: Document the architectural names of our GTIMERs 2025-03-07 10:08:21 +00:00
helper.c target/arm: Define raw write for PMU CLR registers 2025-06-13 11:03:20 +01:00
helper.h target/arm/helper: extract common helpers 2025-05-14 15:12:40 +01:00
hvf-stub.c target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definition 2025-05-29 17:45:10 +01:00
hvf_arm.h target/arm/hvf: Include missing 'cpu-qom.h' header 2025-05-29 17:45:12 +01:00
hyp_gdbstub.c target/arm: Replace target_ulong -> vaddr for HWBreakpoint 2025-05-14 15:12:40 +01:00
idau.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
internals.h target/arm: Replace target_ulong -> vaddr for HWBreakpoint 2025-05-14 15:12:40 +01:00
Kconfig kconfig: express dependency of individual boards on libfdt 2024-05-10 15:45:15 +02:00
kvm-consts.h exec: Rename NEED_CPU_H -> COMPILING_PER_TARGET 2024-04-26 09:49:51 +02:00
kvm-stub.c target/arm/kvm-stub: add missing stubs 2025-05-14 15:12:40 +01:00
kvm.c kvm: Introduce kvm_arch_pre_create_vcpu() 2025-05-28 19:01:40 +02:00
kvm_arm.h target/arm/kvm: Include missing 'cpu-qom.h' header 2025-05-29 17:45:12 +01:00
machine.c target/arm/machine: move cpu_post_load kvm bits to kvm_arm_cpu_post_load function 2025-05-14 15:12:40 +01:00
meson.build target-arm queue: 2025-05-30 11:41:21 -04:00
multiprocessing.h target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header 2024-01-26 11:30:48 +00:00
ptw.c target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw 2025-05-14 15:12:40 +01:00
syndrome.h target/arm: fix exception syndrome for AArch32 bkpt insn 2024-02-02 13:51:57 +00:00
tcg-stubs.c target/arm: Unexport assert_hflags_rebuild_correctly 2025-04-30 12:45:05 -07:00
trace-events target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling 2024-03-07 12:19:03 +00:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
vfp_fpscr.c target/arm: Rename vfp_helper.c to vfp_fpscr.c 2025-02-25 15:32:58 +00:00