Zhenzhong Duan 860bb8b925 hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class ... RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really necessary. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2025-06-10 12:59:09 +02:00
..
boot.c	target/riscv: store RISCVCPUDef struct directly in the class	2025-05-20 08:18:53 +02:00
Kconfig	hw/riscv: Add Microblaze V generic board	2024-12-20 11:22:47 +10:00
meson.build	hw/riscv/riscv-iommu: add riscv-iommu-hpm file	2025-03-04 15:42:54 +10:00
microblaze-v-generic.c	include/system: Move exec/address-spaces.h to system/address-spaces.h	2025-04-23 14:08:21 -07:00
microchip_pfsoc.c	hw/riscv: Configurable MPFS CLINT timebase freq	2025-05-19 13:30:24 +10:00
numa.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
opentitan.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
riscv-iommu-bits.h	hw/riscv/riscv-iommu: Fix process directory table walk	2025-03-19 16:35:58 +10:00
riscv-iommu-hpm.c	hw/riscv: add IOMMU HPM trace events	2025-03-04 15:42:54 +10:00
riscv-iommu-hpm.h	hw/riscv/riscv-iommu: add hpm events mmio write	2025-03-04 15:42:54 +10:00
riscv-iommu-pci.c	hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class	2025-06-10 12:59:09 +02:00
riscv-iommu-sys.c	hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class	2025-06-10 12:59:09 +02:00
riscv-iommu.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
riscv-iommu.h	hw/riscv/riscv-iommu: add hpm events mmio write	2025-03-04 15:42:54 +10:00
riscv_hart.c	target/riscv: Pass ra to riscv_csrrw	2025-05-19 13:39:29 +10:00
shakti_c.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
sifive_e.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
sifive_u.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
spike.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
trace-events	hw/riscv: add IOMMU HPM trace events	2025-03-04 15:42:54 +10:00
trace.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
virt-acpi-build.c	target/riscv: update max_satp_mode based on QOM properties	2025-05-20 08:04:19 +02:00
virt.c	target/riscv: update max_satp_mode based on QOM properties	2025-05-20 08:04:19 +02:00