Christoph Muellner a939c50079 target/riscv: implement Zicboz extension ... The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-03-05 11:49:20 -08:00
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trans_privileged.c.inc	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
trans_rva.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvb.c.inc	target/riscv: fix ctzw behavior	2023-02-07 08:19:23 +10:00
trans_rvd.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvf.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvh.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvi.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2022-06-10 09:31:42 +10:00
trans_rvv.c.inc	target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc	2023-03-01 15:17:56 -08:00
trans_rvzawrs.c.inc	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc	target/riscv: Simplify the check for Zfhmin and Zhinxmin	2023-03-01 14:57:32 -08:00
trans_rvzicbo.c.inc	target/riscv: implement Zicboz extension	2023-03-05 11:49:20 -08:00
trans_rvzicond.c.inc	target/riscv: Add support for Zicond extension	2023-03-01 17:07:59 -08:00
trans_svinval.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_xthead.c.inc	RISC-V: XTheadMemPair: Remove register restrictions for store-pair	2023-03-01 16:59:50 -08:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00