qemu/target
Stefan Hajnoczi c5f122fdcc * ci: enable RISC-V cross jobs
* rust: bump minimum supported version to 1.77
 * rust: enable uninlined_format_args lint
 * initial Emscripten support
 * small fixes
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* ci: enable RISC-V cross jobs
* rust: bump minimum supported version to 1.77
* rust: enable uninlined_format_args lint
* initial Emscripten support
* small fixes

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# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (30 commits)
  gitlab: Enable CI for wasm build
  tests: Add Dockerfile containing dependencies for Emscripten build
  meson: Add wasm build in build scripts
  util: Add coroutine backend for emscripten
  util: exclude mmap-alloc.c from compilation target on Emscripten
  Disable options unsupported on Emscripten
  include/qemu/osdep.h: Add Emscripten-specific OS dependencies
  block: Fix type conflict of the copy_file_range stub
  block: Add including of ioctl header for Emscripten build
  util/cacheflush.c: Update cache flushing mechanism for Emscripten
  include/glib-compat.h: Poison g_list_sort and g_slist_sort
  target/s390x: Fix type conflict of GLib function pointers
  target/ppc: Fix type conflict of GLib function pointers
  target/i386/cpu.c: Fix type conflict of GLib function pointers
  target/arm/helper.c: Fix type conflict of GLib function pointers
  docs: build-system: fix typo
  ci: run RISC-V cross jobs by default
  rust: clippy: enable uninlined_format_args lint
  target/i386/emulate: fix target_ulong format strings
  docs: rust: update for newer minimum supported version
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-07 16:10:59 -04:00
..
alpha accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
arm * ci: enable RISC-V cross jobs 2025-05-07 16:10:59 -04:00
avr accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
i386 * ci: enable RISC-V cross jobs 2025-05-07 16:10:59 -04:00
loongarch accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
m68k accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
microblaze accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
mips accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
openrisc tcg: Define INSN_START_WORDS as constant 3 2025-05-01 07:37:13 -07:00
ppc * ci: enable RISC-V cross jobs 2025-05-07 16:10:59 -04:00
riscv accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
rx accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
s390x * ci: enable RISC-V cross jobs 2025-05-07 16:10:59 -04:00
sh4 accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
sparc accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
tricore accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
xtensa accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00