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The timer controller include 8 sets of 32-bit decrement counters, based on either PCLK or 1MHZ clock and the design of timer controller between AST2600 and AST2700 are almost the same. TIMER0 – TIMER7 has their own individual control and interrupt status register. In other words, users are able to set timer control in register TMC10 with different TIMER base address and clear timer control and interrupt status in register TMC14 with different TIMER base address. Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callback functions and a new ast2700 class to support AST2700. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 = 0x12C1_0000 Base Address of Timer 1 = 0x12C1_0040 Base Address of Timer 2 = 0x12C1_0080 Base Address of Timer 3 = 0x12C1_00C0 Base Address of Timer 4 = 0x12C1_0100 Base Address of Timer 5 = 0x12C1_0140 Base Address of Timer 6 = 0x12C1_0180 Base Address of Timer 7 = 0x12C1_01C0 The register address space of each TIMER is "0x40" , and uses the following formula to get the index and register of each TIMER. timer_index = offset >> 6; timer_offset = offset & 0x3f; The TMC010 is a counter control set and interrupt status register. Write "1" to TMC10[3:0] will set the specific bits to "1". Introduce a new "aspeed_2700_timer_set_ctrl" function to handle this register behavior. The TMC014 is a counter control clear and interrupt status register, to clear the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle this register behavior. TMC014 does not support read operation. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Acked-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250113064455.1660564-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/*
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* ASPEED AST2400 Timer
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef ASPEED_TIMER_H
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#define ASPEED_TIMER_H
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#include "qemu/timer.h"
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#include "hw/misc/aspeed_scu.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_TIMER "aspeed.timer"
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OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
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#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
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#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
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#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
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#define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030"
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#define TYPE_ASPEED_2700_TIMER TYPE_ASPEED_TIMER "-ast2700"
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#define ASPEED_TIMER_NR_TIMERS 8
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typedef struct AspeedTimer {
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qemu_irq irq;
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uint8_t id;
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QEMUTimer timer;
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/**
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* Track the line level as the ASPEED timers implement edge triggered
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* interrupts, signalling with both the rising and falling edge.
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*/
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int32_t level;
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uint32_t reload;
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uint32_t match[2];
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uint64_t start;
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} AspeedTimer;
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struct AspeedTimerCtrlState {
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/*< private >*/
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t ctrl;
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uint32_t ctrl2;
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uint32_t ctrl3;
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uint32_t irq_sts;
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AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
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AspeedSCUState *scu;
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};
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struct AspeedTimerClass {
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SysBusDeviceClass parent_class;
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uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset);
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void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value);
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};
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#endif /* ASPEED_TIMER_H */
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