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a7fc988051
Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220217101924.15347-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25 lines
572 B
C
25 lines
572 B
C
#ifndef HW_MIPS_H
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#define HW_MIPS_H
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/* Definitions for mips board emulation. */
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#include "qemu/units.h"
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/* Kernels can be configured with 64KB pages */
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#define INITRD_PAGE_SIZE (64 * KiB)
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#include "exec/memory.h"
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/* gt64xxx.c */
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PCIBus *gt64120_register(void);
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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/* rc4030.c */
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typedef struct rc4030DMAState *rc4030_dma;
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void rc4030_dma_read(void *dma, uint8_t *buf, int len);
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void rc4030_dma_write(void *dma, uint8_t *buf, int len);
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DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr);
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#endif
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