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The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers directly connected to the APB bus. They can be programmed as master or slave but the propopsed model only supports the master mode. On the TODO list, we also have : - improve and harden the state machine. - bus recovery support (used by the Linux driver). - transfer mode state machine bits. this is not strictly necessary as it is mostly used for debug. The bus busy bit is deducted from the I2C core engine of qemu. - support of the pool buffer: 2048 bytes of internal SRAM (not used by the Linux driver). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1464704307-25178-1-git-send-email-clg@kaod.org [PMM: removed unused functions aspeed_i2c_bus_get_state() and aspeed_i2c_bus_set_state()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37 lines
780 B
C
37 lines
780 B
C
/*
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* ASPEED AST2400 SoC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef AST2400_H
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#define AST2400_H
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#include "hw/arm/arm.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/i2c/aspeed_i2c.h"
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typedef struct AST2400State {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU *cpu;
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MemoryRegion iomem;
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AspeedVICState vic;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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} AST2400State;
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#define TYPE_AST2400 "ast2400"
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#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
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#define AST2400_SDRAM_BASE 0x40000000
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#endif /* AST2400_H */
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