Jonathan Cameron a185ff05fe hw/cxl: Update RAS Capability Definitions for version 3. ... Part of bringing all of CXL emulation inline with CXL r3.1. No functional changes. Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-02-14 06:09:32 -05:00
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cxl.h	hw/cxl/mbox: Add Physical Switch Identify command.	2023-11-07 03:39:11 -05:00
cxl_cdat.h	include/hw/pci: Break inclusion loop pci_bridge.h and cxl.h	2023-01-08 01:54:22 -05:00
cxl_component.h	hw/cxl: Update RAS Capability Definitions for version 3.	2024-02-14 06:09:32 -05:00
cxl_device.h	hw/cxl/device: read from register values in mdev_reg_read()	2024-02-14 06:09:32 -05:00
cxl_events.h	hw/cxl: Line length reductions	2023-11-07 03:39:11 -05:00
cxl_host.h	hw/cxl: Clean up includes	2023-02-08 07:16:23 +01:00
cxl_pci.h	hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt	2023-11-07 03:39:11 -05:00