Bin Meng a9ec1c76d5 riscv: sifive_u: Correct UART0's IRQ in the device tree ... The UART0's interrupt vector is wrongly set to 1 in the device tree. Use SIFIVE_U_UART0_IRQ instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-19 05:18:42 -07:00
..
Kconfig	riscv/Kconfig: enable PCI_DEVICES	2019-03-11 16:33:49 +01:00
Makefile.objs	hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards	2019-02-05 16:50:20 +01:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Fix CLINT timecmp low 32-bit writes	2018-12-20 12:08:43 -08:00
sifive_e.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
sifive_plic.c	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 05:14:39 -07:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	riscv: sifive_u: Correct UART0's IRQ in the device tree	2019-03-19 05:18:42 -07:00
sifive_uart.c	riscv: sifive_uart: Generate TX interrupt	2019-03-19 05:18:28 -07:00
spike.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
virt.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00